Rajendra S. Katti

Achieving network on chip fault tolerance by adaptive remapping

This paper investigates achieving fault tolerance by adaptive remapping in the context of Networks on Chip. The problem of dynamic application remapping is formulated and an efficient algorithm is proposed to address single and multiple PE failures. The new algorithm can be used to dynamically react and recover from PE failures in order to maintain system functionality. The quality of results is similar to that achieved using simulated annealing but in significantly shorter runtimes.

A Secure Identification and Key agreement protocol with user Anonymity (SIKA)

Anonymity is a desirable security feature in addition to providing user identification and key agreement during a users login process. Recently, Yang et al., proposed an efficient user identification and key distribution protocol while preserving user anonymity. Their protocol addresses a weakness in the protocol proposed by Wu and Hsu. Unfortunately, Yangs protocol poses a vulnerability that can be exploited to launch a Denial-of-Service (DoS) attack. In this paper, we cryptanalyze Yangs protocol and present the DoS attack. We further secure their protocol by proposing a Secure Identification and Key agreement protocol with user Anonymity (SIKA) that overcomes the above limitation while achieving security features like identification, authentication, key agreement and user anonymity.

Multiple-output low-power linear feedback shift register design

In this paper, we present a new low-power architecture for linear feedback shift registers (LFSRs) that produces the output of several clock cycles of a serial LFSR at once while reducing the activity factors of the flip-flop outputs. The frequency of operation can thus be reduced by a factor equal to the number of outputs produced at a time. A reduction in the frequency of the LFSR allows for a reduction in the power-supply voltage. Thus, dynamic power dissipation is reduced by up to 93% due to decreases in power-supply voltage, frequency, and the activity factor. Furthermore, the hardware needed for our implementation is far less than previous low-power implementations of both single and multiple-output LFSRs. Our method is also good for built-in self-test (BIST) applications because for most degrees of N it results in all 2/sup N/-1 distinct patterns.

An efficient data-independent technique for compressing test vectors in systems-on-a-chip

We present an efficient approach, namely, pattern run-length (PRL) coding, for reducing the volume of test vectors that must be stored in automatic test equipment (ATE) and transferred to each core in a system-on-a-chip (SOC) during manufacturing test. The need for compressing test data is due to the bandwidth bottleneck between the ATE and the SOC. In our new coding scheme, the test vectors for the SOC are stored in compressed form in the ATE memory and transferred to the chip. An embedded processor is employed to perform decompression. The decompressed test set is then applied to the scan chains of each core-under-test. Pattern run-length coding works by compressing consecutive patterns in an innovative manner. The proposed compression is data-independent. The program for decompression is very small and simple, thereby allowing fast and high throughput to minimize test time. Experimental results for ISCAS-89 benchmarks show that for almost all of the circuits our new technique results in much better compression ratios than former methods.

A new residue arithmetic error correction scheme

Automatic detection and correction of errors in the residue number system involves the conversion of residue representations to integers and base extension. The residue number system is generally restricted to moduli that are pairwise relatively prime. In this paper we consider error detection and correction using a moduli set with common factors. A method to construct a moduli set that leads to simplified error detection and correction is presented. Error detection can now be performed by computing residues in parallel. Error correction does not involve base extension any more. It is also shown that, removing all restrictions on the moduli set, leads to more complex error detection/correction algorithms.

Low complexity multiplication in a finite field using ring representation

Elements of a finite field, GF(2/sup m/), are represented as elements in a ring in which multiplication is more time efficient. This leads to faster multipliers with a modest increase in the number of XOR and AND gates needed to construct the multiplier. Such multipliers are used in error control coding and cryptography. We consider rings modulo trinomials and 4-term polynomials. In each case, we show that our multiplier is faster than multipliers over elements in a finite field defined by irreducible pentanomials. These results are especially significant in the field of elliptic curve cryptography, where pentanomials are used to define finite fields. Finally, an efficient systolic implementation of a multiplier for elements in a ring defined by x/sup n/+x+1 is presented.

A Hash-based Strong Password Authentication Protocol with User Anonymity

Password authentication protocols range from complex public-key cryptosystems to simple hash-based password authentication schemes. One common feature of these protocols is that the user’s identity is transmitted in plain during the authentication process, which allows an attacker to monitor the user’s activities. In many cases, the user’s anonymity is a desirable security feature. In this paper, we propose a hash-based Strong Password Authentication Protocol with user Anonymity (SPAPA). We also analyze the security of our proposed scheme against known attacks.

Left-to-right optimal signed-binary representation of a pair of integers

The common computation in elliptic curve cryptography (ECC), aP + bQ, is performed by extending Shamirs method for the computation of the product of powers of two elements in a group. The complexity of computing aP + bQ is dependent on the joint weight of the binary expansion of positive integers a and b. We give a method of finding a minimum joint weight signed-binary representation of a pair of integers. Our method examines the integers a and b from left to right, thereby making the conversion to signed-binary form compatible with Shamirs method. This reduces the memory required to perform the computation of aP + bQ.

The alternating greedy expansion and applications to computing digit expansions from left-to-right in cryptography

The central topic of this paper is the alternating greedy expansion of integers, which is defined to be a binary expansion with digits {0, ±1} with the property that the nonzero digits have alternating signs. We collect known results about this alternating greedy expansion and complement it with other useful properties and algorithms. In the second part, we apply it to give an algorithm for computing a joint expansion of d integers of minimal joint Hamming weight from left to right, i.e., from the column with the most significant bits towards the column with the least significant bits. Furthermore, we also compute an expansion equivalent to the so-caled w-NAF from left to right using the alternating greedy expansion.

Speeding up elliptic cryptosystems using a new signed binary representation for integers

Two new signed binary representations are presented that simplify hardware or software necessary in elliptic curve cryptosystems. Simplified algorithms are presented for computing the new binary representations. This speeds up elliptic cryptosystems. The algorithms are useful for smart card and digital signature verification applications. The first algorithm computes a new representation for an integer d and speeds up the computation of d/spl times/P, where P is a point on an elliptic curve. The second algorithm computes a new representation for two integers g and h and speeds up the computation of (g/spl times/P)+(h/spl times/Q), where P and Q are points on an elliptic curve.