Xiaoyu Ruan

Multiple-output low-power linear feedback shift register design

In this paper, we present a new low-power architecture for linear feedback shift registers (LFSRs) that produces the output of several clock cycles of a serial LFSR at once while reducing the activity factors of the flip-flop outputs. The frequency of operation can thus be reduced by a factor equal to the number of outputs produced at a time. A reduction in the frequency of the LFSR allows for a reduction in the power-supply voltage. Thus, dynamic power dissipation is reduced by up to 93% due to decreases in power-supply voltage, frequency, and the activity factor. Furthermore, the hardware needed for our implementation is far less than previous low-power implementations of both single and multiple-output LFSRs. Our method is also good for built-in self-test (BIST) applications because for most degrees of N it results in all 2/sup N/-1 distinct patterns.

An efficient data-independent technique for compressing test vectors in systems-on-a-chip

We present an efficient approach, namely, pattern run-length (PRL) coding, for reducing the volume of test vectors that must be stored in automatic test equipment (ATE) and transferred to each core in a system-on-a-chip (SOC) during manufacturing test. The need for compressing test data is due to the bandwidth bottleneck between the ATE and the SOC. In our new coding scheme, the test vectors for the SOC are stored in compressed form in the ATE memory and transferred to the chip. An embedded processor is employed to perform decompression. The decompressed test set is then applied to the scan chains of each core-under-test. Pattern run-length coding works by compressing consecutive patterns in an innovative manner. The proposed compression is data-independent. The program for decompression is very small and simple, thereby allowing fast and high throughput to minimize test time. Experimental results for ISCAS-89 benchmarks show that for almost all of the circuits our new technique results in much better compression ratios than former methods.

Left-to-right optimal signed-binary representation of a pair of integers

The common computation in elliptic curve cryptography (ECC), aP + bQ, is performed by extending Shamirs method for the computation of the product of powers of two elements in a group. The complexity of computing aP + bQ is dependent on the joint weight of the binary expansion of positive integers a and b. We give a method of finding a minimum joint weight signed-binary representation of a pair of integers. Our method examines the integers a and b from left to right, thereby making the conversion to signed-binary form compatible with Shamirs method. This reduces the memory required to perform the computation of aP + bQ.

The alternating greedy expansion and applications to computing digit expansions from left-to-right in cryptography

The central topic of this paper is the alternating greedy expansion of integers, which is defined to be a binary expansion with digits {0, ±1} with the property that the nonzero digits have alternating signs. We collect known results about this alternating greedy expansion and complement it with other useful properties and algorithms. In the second part, we apply it to give an algorithm for computing a joint expansion of d integers of minimal joint Hamming weight from left to right, i.e., from the column with the most significant bits towards the column with the least significant bits. Furthermore, we also compute an expansion equivalent to the so-caled w-NAF from left to right using the alternating greedy expansion.

Data-Independent Pattern Run-Length Compression for Testing Embedded Cores in SoCs

This paper presents a new compression technique for testing the intellectual property (IP) cores in system-on-chips. The pattern run-length compression applies the well-known run-length coding to equal and complementary consecutive patterns of the precomputed test data. No structural information of the IP cores is required by the encoding procedure. A data-independent decompressor can be realized by the embedded processor or on-chip circuitry. The decompressed test set can be flexibly applied to a single-scan or multiple-scan chain of each core-under-test. Experiments on ISCAS-89 benchmarks show that the new technique results in superior compression performance. The test application time is also significantly reduced

Using Improved Shannon-Fano-Elias Codes for Data Encryption

We consider using Shannon-Fano-Elias codes for data encryption. In many applications both compression and security are required. If the cryptanalyst knows the code construction rule and the probability mass function of the source, then Huffman code provides no ambiguity, but Shannon-Fano-Elias coding is a good candidate since the ordering of symbols can be arbitrary in the encoding process, which produces super-exponential complexity for deciphering. Unfortunately, the conventional Shannon-Fano-Elias code has relatively large code length that makes it inefficient. In this paper, we propose two simple algorithms to reduce the expected length of Shannon-Fano-Elias codes. Experimental results on English text show that the proposed methods reduce the length by as much as 23.4%

Cryptanalysis of Shannon-Fano-Elias codes

Data compression techniques such as Shannon-Fano-Elias coding are often used in conjunction with cryptography. We discuss using Shannon-Fano-Elias codes for encryption. We focus mainly on the problem of deciphering a binary sequence that has been Shannon-Fano-Elias encoded. We show that if a cryptanalyst knows the source symbols and the probability mass function (PMF), then the Shannon-Fano-Elias coded sequences may be deciphered within a finite amount of time by exhaustive search. A simple strategy is introduced to prevent this type of eavesdropping

A New Source Coding Scheme with Small Expected Length and Its Application to Simple Data Encryption

We present a new source coding scheme with smaller expected length than Shannon-Fano-Elias codes. The ordering of source symbols input to the proposed encoding algorithm can be arbitrary. We show that this property leads to exponential complexity for eavesdropping even though an adversary knows the code construction rule and the probability mass function of the source

On the signed-binary window method [cryptosystem applications]

We propose a left-to-right (i.e., from the most significant column to the least significant column) algorithm for computing a signed-binary (SB) representation of pairs of integers with minimum joint weight as well as maximum average length of zero-column runs. The proposed method speeds up the scalar multiplication of elliptic curve cryptosystems; (ECC) by all known strategies, while at the same time reduces the hardware overhead. Furthermore, we present the necessary and sufficient condition that an SB representation of n integers has minimum joint weight.

Left-to-right binary signed-digit recoding for elliptic curve cryptography

In this paper we present a new left-to-right (i.e., from the most significant bit to the least significant bit) algorithm to compute the binary signed-digit representations of two integers g and h such that their joint weight is optimal. This method has lower complexity compared to the best known method JSF (Joint Sparse Form) algorithm. This method can be easily extended to the case of finding the signed-digit representation of more than two integers. In [1] Solinas left this as an open problem. Such an algorithm is useful in simplifying the circuits for the implementation of elliptic curve cryptosystems (ECC).