Rajesh Khamankar

Gate length dependent polysilicon depletion effects

Degradation of MOS gate capacitance in the inversion region becomes worse as the gate length is scaled down, according to a new experiment. Namely, the polysilicon depletion effect has gate length dependence. The origin of this gate length-dependent polydepletion effect has been modeled and verified by using device simulation. As a result, the gradient of dopant distribution resulting from ion implantation is shown to be an additional potential drop in the polygate. In addition, the enlarged depletion width at the gate sidewall can worsen the polydepletion effect for very-small MOSFETs.

Dopant profile and gate geometric effects on polysilicon gate depletion in scaled MOS

Polysilicon depletion effects show a strong gate length dependence according to experimental p-channel MOS capacitance-voltage (C-V) data. The effect can be influenced not only by gate geometries, but also by dopant profiles in poly-gates. These effects have been modeled and verified using device simulation. Nonuniform dopant distributions in the vertical and lateral direction in the poly-gate cause additional potential drops. The potential drop in the poly-gate becomes critical as the gate geometry is scaled down due to edge and corner depletions resulting from fringing electric fields.

Impact of post processing damage on the performance of high dielectric constant PLZT thin film capacitors for ULSI DRAM applications

The exposure of PLZT thin films to post deposition processes may have a detrimental effect on the properties of the films. Hence for the proper integration of these films into CMOS technology, these effects need to be studied and improved upon. Fresh devices have been exposed to x-rays, plasma and forming gas anneals. Each of these processes is seen to cause a significant change in the DRAM polarization, leakage current and the reliability properties. An annealing technique has been proposed for a complete recovery in these properties.<<ETX>>

A novel low-temperature process for high dielectric constant BST thin films for ULSI DRAM applications

BST (BaSrTiO/sub 3/) thin films are being widely studied as alternative dielectrics for ULSI DRAM storage capacitors. An important issue involved in the use of these films is related to the process integration with silicon technology. For example the high temperatures at which the films are typically deposited and/or annealed is one of the major concerns. In this paper we demonstrate, for the first time, a new technology whereby high quality BaSrTiO/sub 3/ films are obtained at a temperature as low as 460/spl deg/C without any post deposition anneals. Excellent resistance to electrical stress and post-deposition processing steps are also demonstrated.

Thickness-scaling of sputtered PZT films in the 200 nm range for memory applications

In this paper, we present electrical and material properties of thin films (100 to 400 nm) of magnetron-sputtered ferroelectric PZT for memory applications. The optimal lead-compensation power (and the resulting film composition) is independent of film-thickness. Reduction of film-thickness leads to a reduction in the crystallization temperature (from 700°C for 400 nm films to 575°C for 100 nm films), and yields evidence for a two-step growth of perovskite rosettes. An optimized 100 nm film yields 12 μC/cm2 for 1.5V operation and fatigues by 25% after 1010 unipolar stress cycles.

Effects of electrical stress parameters on polarization loss in ferroelectric P(L)ZT thin film capacitors

The effects of stress parameters (e,g,, stress magnitude, frequency, and pulse shape) on the loss of DRAM polarization during unipolar pulse stressing in sol-gel P(L)ZT thin film capacitors have been studied. The results indicate that there is a strong correlation between the fatigue rate and the DRAM polarization for the fresh device. It has been found that contrary to what one might expect, the fatigue rate does not increase indefinitely with increasing stress voltage but saturates at the same voltage at which the polarization-voltage loop saturates. Though the effect of the rise time of the stress pulses on the fatigue rate is negligible, the fatigue rate is strongly dependent on the pulse width of the trapezoidal stress pulses.<<ETX>>

La doped PZT films for gigabit DRAM technology

Very low leakage current density (5/spl times/10/sup -7/ A/cm/sup 2/ even at 125/spl deg/C) and high charge storage density (100 fCspl mu/m/sup 2/) under V/sub DD2=1 V conditions have been achieved using 5% La doped PZT films for gigabit DRAM capacitor dielectrics. In addition, the fatigue and TDDB measurements indicate good reliability of this capacitor.<<ETX>>

Effects of nonlinear storage capacitor on DRAM READ/WRITE

Important aspects of nonlinear storage capacitor switching and their impact on DRAM READ/WRITE operations are explained using a simple model and PSpice simulation. The voltage signal and charge-transfer rate are found to be dependent not only on the total charged stored, but also on the exact shape of the storage capacitor Q-V curve. Typical paraelectric capacitors are shown to deliver a smaller voltage signal than a linear capacitor that has the same stored charge at the operating voltage. Further, typical paraelectric capacitors have slower READ but faster WRITE compared to the linear capacitor.<<ETX>>

The effect of deposition temperature on the material and electrical properties of PZT thin films for ULSI DRAM applications

Abstract The effects of deposition temperature on the properties of thin films of sputtered lead-zirconate-titanate (PZT) have been studied for ULSI DRAM storage capacitor dielectric applications. The films were deposited by reactive dc magnetron sputtering from a multi-component target. The grain size for the films deposited at 400°C was found to be less than 1000 A, while it was ∼ 10–30 μm for films deposited at 200°C. Small grain-sized material is desirable since it leads to better cell-to-cell uniformity in terms of charge storage capacity and other electrical and reliability properties. The optimum lead compensation was found to increase as the deposition temperature (T dep) increased. Leakage current density stays fairly constant as T dep is varied. As-deposited films, with a deposition temperature of 500°C, were rich in the perovskite phase and showed a high charge storage density of 11.2 μC/cm2 and a low leakage current density of 5.1 × 10−7 A/cm2 (both at 1.5 V). This implies the possibility of e...

Ultra-Thin Sputtered Pzt Films for Ulsi Drams

In this work, a high-temperature deposition technique has been developed for ultra-thin sputtered PZT films for ULSI DRAM ( 2 ) and low leakage current density. An optimized 65nm PZT thin film was found to have an equivalent SiO 2 thickness of 1.9A and a leakage current density of less than 10 −6 A/cm 2 under 2V operation.