Rajesh Mittal

Systematic approach for trim test time optimization: Case study on a multi-core RF SOC

It is well-known that complex SOCs with RF and embedded power management (PM) modules require significant post manufacturing calibration to ensure that the device meets the design specifications. These calibrations are carried out by setting the register bits (which in turn help to finely adjust the parameters of the components inside the module containing these registers), a process commonly termed as trim. Not only must these calibrations precede any other manufacturing test operation, but they also require analog measurements and consume significant ATE resources and hence test time. As a result, it is commonly understood and observed that the calibration trim for such SOCs with embedded RF and PM is often comparable to the SOC test time itself. This paper presents some crucial investigations into one such 45 nm multi-core RF SOC designed at Texas Instruments. Its main contributions are: (i) The various trim operations are analyzed for the incurred test times and incurred ATE resources. (ii) Corresponding to each such operation, trim test time minimization techniques are proposed and experimental data on the accrued benefits is presented. (iii) A comprehensive hardware trim BIST controller is described, which enables trim automation and further optimization in complex SOCs. Together, these investigations provide a recipe for efficiently performing trims in complex mixed-signal SOCs with reduced test times and higher ATE enabled multi-site.

Towards adaptive test of multi-core RF SoCs

This paper discusses how adaptive test techniques can be applied to multi-core RF SoCs, together with design implementation and test challenges. Various techniques specific to RF circuits covering calibration trims, power management modules, co-existence issues, concurrent testing, and test measurements are explained. Results on different designs are presented. Together, they highlight the need and scope of adaptive test for RF circuits, and share a new dimension in the test of multi-core circuits, under different constraints of design, test and test equipment.

Modified flip-flop architecture to reduce hold buffers and peak power during scan shift operation

Hold timing closure and scan power are major concerns for any design. Hold closure for scan shift operation generally causes addition of buffers in the data path between flip-flops. This results in increased gate count that will toggle during the functional mode of operation thereby resulting in an increase in functional power. Scan operation also causes higher switching activity due to high toggling in a given test cycle. There are two components of power i.e. peak power and average power. Peak power increases IR-drop in the design, thereby reducing the voltage across the transistor and can lead to failure. In this paper we will present a modified flip-flop architecture that will serve two purposes i.e. enabling hold timing closure across process, voltage, temperature and reducing peak power during scan shift operation with minimal impact to functional timing and area. The modified flip-flop will introduce a half cycle delay in the data path invariant of process, voltage, temperature thereby easing hold closure. Test time and coverage are not impacted by the same. Existing ATPG tool generated pattern can be applied with this scheme. This approach reduces peak power close to 50% and reduces hold buffer area close to 40% in a given design.

Circuit and DFT techniques for robust and low cost qualification of a mixed-signal SoC with integrated power management system

This paper discusses some specific circuit, and analog DFT techniques and methodologies used in integrated power management (PM) systems to overcome challenges of mixed-signal SoC qualification. They are mainly targeted at achieving the following: 1. Enabling the robust digital and system level test and burn-in (BI) with external supplies by disabling the on-chip PM with robust power-on performance, 2. Minimising external on-board active components in BI board and making the whole BI process more robust, 3. Making the IDDQ tests more robust, increasing the IDDQ sensitivity by less error prone design methods and enabling IDDQ tests possible on analog supplies, and 4. Defining separate BI strategy for the whole PM modules on-chip and enabling it by targeted analog test modes.

Tutorial T10: Post - Silicon Validation, Debug and Diagnosis

Summary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. Drastic increase in design complexity along with the emergence of new failure mechanisms in the nanometer regime has led to significant increase in the complexity of verification, validation, and debug of integrated circuits. In spite of extensive efforts, it is not always possible to detect all the functional errors and electrical faults during pre-silicon validation. Post-silicon validation is used to detect design flaws including the escaped functional errors as well as electrical faults. In this tutorial, we will provide a comprehensive coverage of both fundamental concepts and recent advances in post-silicon validation, debug and diagnosis. The tutorial presenters (3 industry experts and 3 faculty members) will provide unique perspectives on both academic research and industrial practices. First, we will discuss various challenges associated with post-silicon validation and debug. Next, we will describe various techniques for automated generation of directed tests to activate both functional errors and electrical faults. We will cover recent advances in observability enhancement through signal selection and low-overhead trace hardware design. We will also describe various state-of-the-art post-silicon debug approaches for modern microprocessors and SoC designs. Next, we will present examples of real-life design failures, and successful debug scenarios in industrial settings. Finally, we will conclude the tutorial with discussion on emerging issues and future directions for successful postsilicon validation and debug.

Test time reduction using parallel RF test techniques

Wireless connectivity SOCs integrate multi-band radios on a single chip. Examples include WLAN 802.11 (“A” band or “BG” band), Bluetooth, Global Positioning System (GPS) and FM (Frequency Modulation) transmitters and receivers. It has been observed the cost of testing these RF components constitutes about 40% of the total cost of testing such an SOC. Reduction of this test cost is, therefore, important. The usage of multiple radios on a single chip provides the option of testing all of them concurrently. The unique functionality and different frequency bands of these radio modules however, prevent blind (unconstrained) parallelism, something which is ubiquitously possible for digital logic and memory modules. Additionally, the ability to test multiple dies in parallel (multi-site testing) and the ability to adopt low-cost tester platforms must also be considered. In this presentation, a case study of a complex SOC with four such radio modules is presented. It is shown how their concurrent test can be planned, together with high levels of multi-site with a low-cost tester platform. Various considerations and tradeoffs in the adoption of this solution are discussed, keeping in mind co-existence and coupling issues when these radios operate in parallel. The software BIST solution (where firmware is executed on a host processor inside the RF module) used to enable such concurrency is also explained, together with the design support required.