Rubin A. Parekhji

Concurrent error detection using monitoring machines

In circuits implementing system level functions, the correctness of the overall operation is critically dependent on the correctness of the control part. Therefore, concurrent error detection techniques for controllers implemented in integrated circuits have previously received wide attention. This paper presents a new technique for concurrent error detection in finite state machine (FSM) controllers. It is based on the use of monitoring machines. In a monitored FSM controller, an auxiliary monitoring machine operates in lock-step with the main FSM, such that any fault in either of the two machines is immediately detected. It is shown how the monitoring machine provides a uniform mechanism for the detection of stuck-at faults as well as delay faults. Besides being less costly than the main machine, it is also not identical to it. These features yield designs which compare very favourably with previous implementations. Not only is the fault coverage higher, also the hardware cost of the monitored sequential circuit is significantly lower.

A Methodology for Designing Optimal Self-Checking Sequential Circuits

This papcl . presents a formal framework for designing self-checking sequen,tial circuits implemented using the monitoriry machine approach. The two main contributions of this paper are: (1) the formulation of the problcm of &;signing an optimal monitoring machine for arbitrcwy fault m,odcls as the problem of minimizi n g an incompletely specified sequential machine, and (2) rlc?iclopin,g a methodology for performing state assignment which results in the monitoring machine hauiruj (L fized number of states for specific fault models. Thx method allows the designer to ezplorc the tradeofl8 between the cost of implementing the main machine and the mon,itoring machine.

Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands

In order to provide high performance with low power consumption, many multicore chips employ dynamic voltage scaling and voltage islands that operate at multiple power-supply voltage levels. Effective defect screening for such chips requires test applications at different operating voltages, which leads to higher test time and test cost compared to systems-on-a-chip (SoCs), which operate at only a single voltage level. We propose test scheduling techniques to minimize the testing time for multicore chips when each core is tested at multiple voltage levels and when it is tested for state retention when the core switches between two voltage levels. The proposed techniques include exact optimization based on integer linear programming and fast heuristic methods. Experimental results for two test-case SoCs from the industry highlight the effectiveness of the proposed method.

Methodology for low power test pattern generation using activity threshold control logic

This paper proposes a new technique of power-aware test pattern generation, wherein the test mode power constraints are specified using pseudo hardware logic functions (referred to as power constraint circuits) that augment the target circuit fed to the ATPG tool. The novelty of this approach is three-fold: (i) The ATPG tool only sees the enhanced circuit. This influences the generation of the test cubes themselves, as against post-processing of these cubes for a given pattern. (ii) Pattern generation can be driven to minimize test power according to a programmable switching activity threshold, and hence, is scalable. (iii) The same constraint circuit can also be effectively used for pattern filtering to isolate patterns which cause high switching activity. Additionally, the proposed method does not require any changes to the pattern generation tool or process. This paper describes the methodology, together with techniques for realizing the hardware circuit and specifying thresholds. Experimental results on various benchmark circuits (including an industrial design) are presented to show the effectiveness of this approach.

A generic low power scan chain wrapper for designs using scan compression

Shrinking power budgets in low power system-on-chips (SoCs) have elevated test power consumption as a major consideration for chip design and test engineering teams. Many traditional automatic test pattern generation (ATPG) and design-for-test (DFT) techniques for test power reduction are either effective for circuits not using test data compression hardware or have implications on the physical design cycle. This paper describes a technique for reducing peak current during scan based testing that can work in the presence of compression, and impose no restrictions on physical design, e.g. related to chip clocking. We propose low-design effort modifications to the test compression logic (wrapper-like changes) that enable us to (a) bypass scan chains or groups of them and (b) shift in constant values into the bypassed flip-flops for lowering the instantaneous current drawn. The modifications are easily localized to a scan chain wrapper that can be used with any scan compression solution. An SoC using lowpower scan chain wrappers provides sufficient configurability (scan chains bypassed or scan chains included) to explore different power reductions with test cost trade-offs. We describe a methodology that allows us to manage the inherent configurability available in our solution. For empirical validation, we have implemented low-power scan chain wrappers for a subset of scan chains in a recently taped-out 65nm low-power SoC. We present experimental data from ATPG and initial silicon power measurements for this chip to demonstrate the benefits and limitations of the proposal.

An efficient test data reduction technique through dynamic pattern mixing across multiple fault models

ATPG tool generated patterns are a major component of test data for large SOCs. With increasing sizes of chips, higher integration involving IP cores and the need for patterns targeting multiple fault models for better defect coverage in newer technologies, the issues of adequate coverage and reasonable test data volume and application time dominate the economics of test. We address the problem of generating compact set of test patterns across multiple fault models. Traditional approaches use separate ATPG for each fault models and minimize patterns either during pattern generation through static or dynamic compaction, or after pattern generation by simulating all patterns over all fault models for static compaction. We propose a novel ATPG technique where all fault models of interest are concurrently targeted in a single ATPG run. Patterns are generated in small intervals, each consisting of 16, 32 or 64 patterns. In each interval fault model specific ATPG setups generate separate pattern sets for their respective fault model. An effectiveness criterion then selects exactly one of those pattern sets. The selected set covers untargeted faults that would have required the most additional patterns. Pattern generation intervals are repeated until required coverage for faults of all models of interest is achieved. The sum total of all selected interval pattern sets is the overall test set for the DUT. Experiments on industrial circuits show pattern count reductions of 21% to 68%. The technique is independent of any special ATPG tool or scan compression technique and requires no change or additional support in an existing ATPG system.

Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands

In order to provide high performance with low power consumption, modern multicore chips employ dynamic voltage scaling and voltage islands that operate at multiple power-supply voltage settings. Effective defect screening for the embedded cores in such multicore chips requires test application at their different operating voltages, which leads to higher test time and test cost. We propose a fast heuristic test scheduling technique for multicore chips that minimize the testing time when each core is tested at multiple voltage settings as well as if it is tested for state retention when the core switches between two voltage levels. Experimental results for two test-case SOCs from industry highlight the effectiveness of the proposed method.

Low Power Test for Nanometer System-on-Chips (SoCs)

Shrinking power consumption budgets and increasing use of low power design techniques in nanometer designs are forcing test engineers to examine the two problems of (a) reducing power consumption in the test mode of circuit operation, and (b) testing the device in the presence of various power management structures. This paper examines the various concerns associated with this domain (often referred to as low-power or power-aware test), identifies the relevant design and test challenges, surveys salient solutions along with the associated trade-offs, and identifies open topics that require further attention from researchers in both academia and industry.

On-chip Test and Repair of Memories for Static and Dynamic Faults

In addition to static faults, dynamic faults are increasingly important for high density embedded memories due to aggressive design rules and shrinking feature sizes. Not only is the test of these faults important, their repair is important too for devices where the yield loss due to memory fails is significant. Dynamic faults can impact one or more memory cells. In the case of the latter, it is also important to diagnose the cell causing the fault, and hence to be repaired. This paper describes an on-chip test and repair solution for static and dynamic faults in random access memories. The main contributions of this paper are three fold: (i) development of new algorithms for detection of static and dynamic faults, and for identification of faulty aggressor cells, (ii) extension of fault syndromes for diagnosis and location of aggressor cells, and (iii) development of an on-chip test, analysis and repair solution implementing these algorithms. It is shown how the proposed fault detection algorithms and redundancy analysis schemes are superior to existing ones for analysis time, hardware overhead, fault coverage and aggressor location capability

Power Analysis and Reduction Techniques for Transition Fault Testing

This paper examines the differences in power consumption characteristics of two popular ATPG techniques for transition fault testing (TFT) -- launch off shift (LOS) and launch off capture (LOC). These differences have critical implications on the circuit switching during the launch and capture cycles, and if unaddressed, can lead to IR drop issues and unwarranted silicon failures. Our investigations show that power consumption in the launch cycle for LOS patterns can be as high as 1.96 times the corresponding number for LOC patterns. We systematically understand the reasons for this difference and propose a variety of power-aware design-for-test (DFT) and automatic test pattern generation (ATPG) techniques to limit this power differential as well as general TFT power consumption. The proposed techniques include use of (a) fill techniques, (b) intelligent test and functional enable control of clock gates, and (c) pattern re-generation using low compression and low effort ATPG. Our experiments demonstrate the efficacy of the proposed techniques in reducing power consumption, and the associated trade-offs in pattern volume.