Rakesh Bhatnagar

Test for detection and location of intermittent faults in combinational circuits

Faults in combinational circuits are either permanent or intermittent. Intermittent faults tend to be environment-dependent; hence altering the environment might rectify these faults. These faults can be detected by applying random input-vectors (IV). The existence of random intermittent faults might require applying more random IV before detection. The detection of permanent faults requires fewer random IV but correction demands location and replacement of the faulty device, if repair is not feasible. Thus correction of a permanent fault costs more than that of an intermittent fault. The correction cost can be reduced by detecting the type of fault. Since most operational failures in a circuit are due to intermittent faults, it is very important to detect the type of fault in order to find a cheaper solution. This paper discusses the behavior of permanent and intermittent faults in combinational circuits, and introduces a test-detection model (TDM) for these faults. The error latency for an intermittent fault is derived. Two test-strategies are intermixed in the model: random testing for fault-detection, and deterministic testing for deciding on the type of fault. The activity of intermittent faults that requires the minimum number of IV for detection is emphasized. Simulation is used to demonstrate the validity of TDM. Although the variables required in TDM can be difficult to evaluate, estimation of their values is not impossible. A worst-case analysis can always be adopted, where variables are easily evaluated, to find an upper bound on the error latency; thus detection of an intermittent fault is assured with a very high probability. The cost-saving offered by intermittent-fault corrections shows the practical aspect of TDM.

Modification of scheduled data flow graph for on-line testability

Abstract An approach to modify a given scheduled data flow graph (SDFG) for improving on-line testability of a data path is presented. Each functional unit (FU) of a data path is tested at least once in a time frame called pass. The approach utilizes idle-time of FUs. A given SDFG is utilized to estimate the number of FUs and their idle periods in which certain operations, called idle-time operations, are scheduled. Modified SDFG is utilized by our FU allocation technique presented earlier that minimizes the testing time. Addition of idle-time operations improves the testability without affecting FUs’ count. The technique yields promising results.

Module allocation for on-line testing

Abstract This article presents a module allocation technique for the synthesis of on-line (concurrent) testable data path from a given scheduled data flow graph. The modules are considered as multi-type, to which more than one type of operation is assigned. The on-line testing is carried out by capturing selective input and output variables of a circuit under test in time frames called passes. The captured variables are shifted out serially to a testing unit, where verification is carried out. An error is detected if any discrepancy is found. The objective is to test each module of the circuit under test for all types of operations assigned to the module. The testing time can be reduced by minimizing the number of variables needed to be shifted out to test all modules. The module allocation is performed with the objective of minimizing the number of modules and the number of variables needed to test these modules. A graph-oriented approach has been employed. Our technique is implemented on different benchmark examples, and the results show an improvement in the testing time, while requiring the minimal number of modules for synthesis.

Concurrent testing in high level synthesis

Abstract A new methodology to incorporate concurrent testing in high level synthesis is presented. Optimization techniques in VLSI designs tend to reduce the idle time of resources in which case the proposed methodology is found extremely useful. The objective is to test each functional unit (FU) of a circuit under test (CUT) at least once in a time frame called pass. Testing is performed continuously by repeating the pass. We carry out the testing by shifting out selective variables of the CUT to an external-testing unit for verification. An additional pin is employed to shift out the variables. Testing time is reduced by minimizing the number of variables needed to be shifted out, which is achieved by an FU allocation technique. The FU allocation utilizes a given scheduled data flow graph as input. Proposed testing methodology, and FU allocation technique, are presented. Results of implementation of the technique, on different benchmark examples, are presented.

Module allocation with idle-time utilization for on-line testability

Abstract This paper presents a module allocation technique to improve on-line testability of a data path. The technique assigns multi-type operations to modules. Types of modules and count of each type of module, needed to synthesize a given scheduled data flow graph (SDFG) must be known a priori. The testing utilizes idle time of modules. The objective is to test each type of operation assigned to a module. Testing time is reduced by minimizing the number of types of operations assigned to a module. Certain operations called idle-time operations are scheduled in the SDFG and assigned to modules in their idle time to enhance testing. Ideally, one idle-time operation is required for each type of operation assigned to the module. The technique minimizes number of types of operations assigned to each module and creates sufficient idle time. Promising results are obtained on benchmark examples.

Modeling and testing for stuck faults in pseudo nMOS combinational circuits

In this paper, a new transistor model is developed. This model employs the logic transistor function (LTF) to examine the behavior of pseudo nMOS logic circuits. The LTF is a Boolean representation of the circuit output in terms of its input variables and its transistor topology. The LTF is automatically generated using the path algebra technique. The faulty behavior of the circuit can be obtained from the fault free LTF by using a systematic procedure. The model assumes the following logic values (0, 1, I, M). I and M imply an intermediate logical value and a memory element, respectively. Both classical stuck-at faults and non classical transistor stuck faults are analyzed in the model. An algorithm that is based on a modified version of the Boolean difference technique is applied to obtain test vectors. Primitive D-cubes of the fault are extracted for a specified sub circuit. To generate test for single or multiple faults, a variant of the D-algorithm may be used.

On-line testable data path synthesis for minimizing testing time

Abstract This paper presents an on-line testable data path synthesis with the perspective of minimizing testing time. Two algorithms are proposed: (a) an independent time constrained scheduling with module allocation; (b) an integrated resource constrained scheduling with module allocation. The algorithms take any behavioral description represented as a data flow graph as input and generate a data path. The data path is composed of resources like modules, registers and multiplexers. Our on-line testing methodology applies to modules where multi-type operations are assigned. The test is performed on each type of operation assigned to a module. The testing time is minimized by minimizing the overall number of types of operations assigned to modules. Thus, our objective is to minimize the overall number of types of operations assigned to all modules by performing data path synthesis. Promising results are obtained on benchmark examples.

Modeling for stuck faults in cmos non-threshold logic (NTL) combinational circuits

Abstract In this paper, a transistor model is presented for CMOS Non Threshold Logic (NTL) combinational circuits. This model employs the logic transistor function (LTF) to examine the behavior of CMOS Non Threshold Logic (NTL) circuits. The LTF is a Boolean representation of the circuit output in terms of its input variables and its transistor topology. The LTF is automatically generated using the path algebra technique. The faulty behavior of the circuit can be obtained from the fault free LTF by using a systematic procedure. The model assumes the logic values 0, 1, I , M, where, I and M imply an intermediate logical value and a memory element, respectively. Both classical stuck-at faults and non classical transistor stuck faults can be analyzed by this model. Primitive D-cubes of the fault can be extracted for a specified subcircuit. To generate test for single or multiple faults, a variant of the D-algorithm may be used. Algorithms that were developed for Pseudo NMOS combinational circuits can be directly applied to generate test vectors.

Modelling and fault detection in microelectronic technologies

The modelling and testing of microelectronic circuits for different technologies are presented. Rapid developments in these technologies have compelled the issue of reliability to become extremely important, A study of these developments, the commonly used microelectronic technologies, the causes of their failures and the circuit models are presented. The circuits are modelled at either the gate level or at the transistor level. Transistor-level modelling is given more emphasis because of some shortcomings in gate-level modelling. The transistor-level model assumes four logic values (0, 1, I, M), where I and M imply an intermediate logical value and a memory element, respectively. Both classical stuck-at faults and non-classical transistor stuck faults can be analysed using the model. An algorithm that is based on a modified version of the Boolean difference technique is applied to obtain test vectors. Primitive D-cubes of the fault are extracted for the specified subcircuit. To generate tests for single or multiple faults, a variant of the D-algorithm may be used.

Power-constrained testing for bridging and stuck short faults in CMOS combinational circuits

An increasing demand for the portable applications has elevated power consumption to be the most critical parameter. A transistor level model and a testing methodology are presented for detected bridging and stuck short faults in CMOS combinatorial circuits, with the power consumption as a major constraint during testing. The circuits are modeled by the CTF (Current Transfer Function) model. The quiescent current (IDDQ) measurement technique is utilized as the testing methodology. Transistor stuck open faults, that can change the test vector for IDDQ, are incorporated in the model. Simulation using hspice is carried out to support the results.