Asad A. Ismaeel

Test for detection and location of intermittent faults in combinational circuits

Faults in combinational circuits are either permanent or intermittent. Intermittent faults tend to be environment-dependent; hence altering the environment might rectify these faults. These faults can be detected by applying random input-vectors (IV). The existence of random intermittent faults might require applying more random IV before detection. The detection of permanent faults requires fewer random IV but correction demands location and replacement of the faulty device, if repair is not feasible. Thus correction of a permanent fault costs more than that of an intermittent fault. The correction cost can be reduced by detecting the type of fault. Since most operational failures in a circuit are due to intermittent faults, it is very important to detect the type of fault in order to find a cheaper solution. This paper discusses the behavior of permanent and intermittent faults in combinational circuits, and introduces a test-detection model (TDM) for these faults. The error latency for an intermittent fault is derived. Two test-strategies are intermixed in the model: random testing for fault-detection, and deterministic testing for deciding on the type of fault. The activity of intermittent faults that requires the minimum number of IV for detection is emphasized. Simulation is used to demonstrate the validity of TDM. Although the variables required in TDM can be difficult to evaluate, estimation of their values is not impossible. A worst-case analysis can always be adopted, where variables are easily evaluated, to find an upper bound on the error latency; thus detection of an intermittent fault is assured with a very high probability. The cost-saving offered by intermittent-fault corrections shows the practical aspect of TDM.

The probability of error detection in sequential circuits using random test vectors

In this article a method is presented for evaluating the probability of detecting (PD) a single stuck-fault in a sequential circuit as a function of the number of random input test vectors. A discrete parameter Markov-model is used in the analysis to obtain closed-form expressions for PD. The circuit is partitioned into three parts, the input and output combinational logic and the memory. The analysis is based upon the stationary-state transition matrix associated with a circuit, and the probability that a fault in one of the partitions produces an error at the output of that partition when a random input vector is applied. Results are presented to show how this problem can be reduced to that of testing an equivalent combinational circuit.

Assignment and allocation of highly testable data paths under scan optimization

Abstract This paper addresses the synthesis of highly testable data paths under scan optimization from a given scheduled data flow graph. The synthesis uses an intelligent register allocation technique to minimize the number of sequential loops. Sequential loops in a data path cause poor testability and the complexity of test generation grows exponentially with the number of sequential loops. The register allocation technique also identifies certain registers in the synthesized data path as scan registers to break the sequential loops. The synthesis also uses an interconnect allocation scheme which optimizes for the number of multiplexer inputs. Our main objective is to eliminate or minimize the number of sequential loops and to identigy minimum number of scan registers to break these loops. Thus, the synthesized data path is free of sequential loops, highly testable and has a low scan register cost overhead. Our technique is verified on different benchmark examples and the results are promising.

Modification of scheduled data flow graph for on-line testability

Abstract An approach to modify a given scheduled data flow graph (SDFG) for improving on-line testability of a data path is presented. Each functional unit (FU) of a data path is tested at least once in a time frame called pass. The approach utilizes idle-time of FUs. A given SDFG is utilized to estimate the number of FUs and their idle periods in which certain operations, called idle-time operations, are scheduled. Modified SDFG is utilized by our FU allocation technique presented earlier that minimizes the testing time. Addition of idle-time operations improves the testability without affecting FUs’ count. The technique yields promising results.

A stuck fault model for dynamic CMOS combinational circuits

Abstract This paper utilizes the logic transistor function (LTF), that was devised to model the static CMOS combinational circuits at the transistor and logic level, to model the dynamic CMOS combinational circuits. The LTF is a Boolean representation of the circuit output in terms of its input variables and its transistor topology. The LTF is automatically generated using the path algebra technique. The faulty behavior of the circuit can be obtained from the fault-free LTF using a systematic procedure. The model assumes the following logic values (0, 1, I, M), where I, and M imply an indeterminate logical value, and a memory element, respectively. The model is found to be efficient in describing a cluster of dynamic CMOS circuits at both the fault-free and faulty modes of operation. Both single and multiple transistor stuck faults are precisely described using this model. The classical stuck-at and non classical stuck open and short faults are analyzed. A systematic procedure to produce the fault-free and faulty LTFs for different implementations of the dynamic CMOS combinational circuits is presented.

Module allocation for on-line testing

Abstract This article presents a module allocation technique for the synthesis of on-line (concurrent) testable data path from a given scheduled data flow graph. The modules are considered as multi-type, to which more than one type of operation is assigned. The on-line testing is carried out by capturing selective input and output variables of a circuit under test in time frames called passes. The captured variables are shifted out serially to a testing unit, where verification is carried out. An error is detected if any discrepancy is found. The objective is to test each module of the circuit under test for all types of operations assigned to the module. The testing time can be reduced by minimizing the number of variables needed to be shifted out to test all modules. The module allocation is performed with the objective of minimizing the number of modules and the number of variables needed to test these modules. A graph-oriented approach has been employed. Our technique is implemented on different benchmark examples, and the results show an improvement in the testing time, while requiring the minimal number of modules for synthesis.

Concurrent testing in high level synthesis

Abstract A new methodology to incorporate concurrent testing in high level synthesis is presented. Optimization techniques in VLSI designs tend to reduce the idle time of resources in which case the proposed methodology is found extremely useful. The objective is to test each functional unit (FU) of a circuit under test (CUT) at least once in a time frame called pass. Testing is performed continuously by repeating the pass. We carry out the testing by shifting out selective variables of the CUT to an external-testing unit for verification. An additional pin is employed to shift out the variables. Testing time is reduced by minimizing the number of variables needed to be shifted out, which is achieved by an FU allocation technique. The FU allocation utilizes a given scheduled data flow graph as input. Proposed testing methodology, and FU allocation technique, are presented. Results of implementation of the technique, on different benchmark examples, are presented.

Stuck fault test generation for dynamic CMOS

Abstract In this paper, a procedure that utilizes a previously introduced LTF model is used to detect classical and non-classical faults. Logic Transistor Function (LTF) was devised to model the dynamic CMOS combinational circuit at the transistor-logic level. The LTF is automatically generated using the path algebra technique. The faulty behavior of the circuit can be obtained from the fault-free LTF. The model uses four logic levels (0,1,M,I) where I and M imply an indeterminate logical value and a memory element, respectively. A systematic procedure is presented to produce the faulty D-cube for a faulty dynamic CMOS gate, by using LTF technique. For test generation algorithm, a variant of the D-algorithm is applied to sensitize the fault effect to an observable output. Both combinational and sequential D-cube may be conceived by using this procedure.

Module allocation with idle-time utilization for on-line testability

Abstract This paper presents a module allocation technique to improve on-line testability of a data path. The technique assigns multi-type operations to modules. Types of modules and count of each type of module, needed to synthesize a given scheduled data flow graph (SDFG) must be known a priori. The testing utilizes idle time of modules. The objective is to test each type of operation assigned to a module. Testing time is reduced by minimizing the number of types of operations assigned to a module. Certain operations called idle-time operations are scheduled in the SDFG and assigned to modules in their idle time to enhance testing. Ideally, one idle-time operation is required for each type of operation assigned to the module. The technique minimizes number of types of operations assigned to each module and creates sufficient idle time. Promising results are obtained on benchmark examples.

Scheduling and variable binding for improved testability in high level synthesis

Abstract In this paper, we present a scheduling and a variable binding technique for improved testability in high level synthesis. The scheduling technique called cost based scheduling system (CBSS), is time constrained which minimizes the number of resources (operations) and the number of registers based on a cost function. The CBSS improves the life time of primary input and primary output variables, reduces the life times of intermediate variables and hence improves the controllability and observability. The testability of the register transfer level (RTL) structure generated by this schedule is therefore improved. CBSS considers all the variables and operations jointly for scheduling. CBSS supports various scheduling modes such as multicycled and chained operations, and pipelining. The complexity of our scheduling algorithm is O(c·n2) where c is the number of control steps and n is the number of operations to be scheduled. To generate a highly testable RTL structure, the CBSS is followed by a variable binding technique to bind the variables into registers. An integer linear programming (ILP) approach is proposed with an objective function that minimizes the number of registers and a set of constraints that improves the testability of the RTL structure. Various case studies are presented and the results on different benchmark examples show the potential of our approach.