Rakesh Kumar Palani

High linearity PVT tolerant 100MS/s rail-to-rail ADC driver with built-in sampler in 65nm CMOS

A novel completely inverter-based ADC driver is proposed that relaxes the gain and unity gain bandwidth requirements of the negative feedback loop by making it not see the closed loop gain. This ADC driver has a built-in first order anti alias filter and uses a passive amplifier to provide a rail-to-rail sampled output signal. This design exploits the linearity of current mirrors and achieves 65dB of linearity at the Nyquist rate for a rail-to-rail output. A semi-constant current biasing circuit for inverters has been proposed to minimizing PVT variations in lower technologies. As a proof of concept an ADC driver is designed and implemented in TSMCs 65nm GP CMOS technology. The measured design operates at 100MS/s and has an OIP3 of 40dBm at the Nyquist rate, provides a gain of 8, and samples the signal onto a 1pF output capacitance while drawing 2mA from a 1V supply.

A 1.56mW 50MHz 3rd-order filter with current-mode active-RC biquad and 33dBm IIP3 in 65nm CMOS

A novel inverter-based-integrator filter design is proposed that relaxes the UGB requirement of the OTAs by decoupling the integration capacitance from the feedback loop. The proposed scheme allows the entire filtering operation to take place in the current domain reducing power supply limitations. Further, in the design the load acts as the compensation capacitance to the OTAs allowing the majority of the current to flow into the load, increasing the overall power efficiency. As a proof of concept, a 3rd order lowpass filter is designed and implemented in an IBM 65nm CMOS process. The measured prototype designed for a 50MHz bandwidth achieves an IIP3 of +33dBm and 1.8X better FOM over state-of-art while drawing 1.3mA from a 1.2V supply, is capable of driving a lpF load, and occupies 6X smaller area.

A throughput-agnostic 11.9–13.6GOPS/mW multi-signal classification SoC for cognitive radios in 40nm CMOS

A blind classification SoC for cognitive radios, featuring multi-signal channelization, 16-core dynamic parallelism-frequency scaling and GALS-based multithreading, is realized in 40nm CMOS. Targeting ≥95% detection probability and <; 0.5% false-alarm rate, the SoC achieves a throughput-insensitive energy efficiency of 11.9-13.6GOPS/mW for multiple 7.8-125MHz bandwidth-agnostic signals in a 500MHz channel. The SoC shows 2.1× lower energy, >2.7× less efficiency variation, 1.2× baseband area and up to 4× processing time reduction compared to prior work. Throughput-matched scheduling of spatial resources enables operation at peak energy efficiency without the need for any voltage adjustment.

An eight channel analog-FFT based 450MS/s hybrid filter bank ADC with improved SNDR for multi-band signals in 40nm CMOS

We present a fully integrated hybrid filter bank ADC based on an analog-FFT geared for baseband signal processing in wireless receivers. The design consists of an 8-point A-FFT for an analysis filter bank, a VGA bank and a sub-ADC bank in the analog domain, and an inverse VGA bank, calibration and inverse FFT for the synthesis filter in the digital domain. The proposed structure enables the signals in each channel of the 450MHz wide band system to be separately digitized using the full dynamic range of the ADC. The prototype is implemented in TSMCs 40nm CMOS GP process. A hybrid filter bank ADC does not have a constant average noise floor and is best used when both large and small signals are present. After calibration, the reconstructed signal with an asymmetric (40dB difference) two tone input, i.e., one large at 1MHz and one small at 225.05MHz shows 55.7dB of image rejection. The SNDR of the smaller signal improves by 6.0dB in comparison to a non-channelized ADC. The total power consumption for both the analog and digital sections is 90.4mW. As far as we are aware this is the first integrated implementation of the full hybrid filter bank principle.

Design of PVT tolerant inverter based circuits for low supply voltages

The design of differential pair based OTAs is becoming increasingly difficult in finer geometries due to lower supply voltages. Inverter based designs have proven to have better transconductance efficiency, higher swing and better linearity but have degraded CMRR, worse PSRR and limited PVT tolerance. In this tutorial, we discuss traditional amplifiers and why inverter based amplifiers are better suited for lower supplies. We then describe the design procedure for inverter based OTA designs with an emphasis on improving their performance, including PVT tolerance, CMRR and PSRR. In particular, we introduce new biasing techniques for inverters to improve their PVT tolerance. We finally validate our designs using measurement results from a number of fabricated designs.

Wideband blind signal classification on a battery budget

A wideband signal sensor is an essential component to enable cognitive radio and dynamic spectrum access techniques, providing real-time detection and modulation classification in a wideband environment of interest. The problem is challenging, requiring a processing suite incorporating detection, estimation, and classification, with stringent power objectives to enable widespread use in untethered battery powered devices. This article provides an overview of an integrated system-on-chip extremely low-power solution, including a wideband mixed-signal front-end, an algorithm suite that incorporates a blind hierarchical modulation classifier, and an ASIC implementation that employs dynamic voltage-frequency scaling and parallel processing that achieves measured energy efficiency ranging between 11.9 GOPS/mW and 13.6 GOPS/mW for full channel feature extraction, resulting in power consumption of 20.1-22.6 mW depending on the number of signals and signal bandwidth. The system bandwidth is selectable at 5, 50, and 500 MHz; in the 500 MHz case an efficient analog 8-point FFT channelizer relaxes the A/D requirement. The sensor can blindly detect and process up to 32 concurrent non-overlapping signals, with a variety of signal characteristics including single- vs. multi-carrier discrimination, carrier detection and estimation, and modulation classification.

A 220-MS/s 9-Bit 2X Time-Interleaved SAR ADC With a 133-fF Input Capacitance and a FOM of 37 fJ/conv in 65-nm CMOS

This brief presents a 9-bit 2X time-interleaved successive approximation (SAR) analog-to-digital converter (ADC) for high-speed applications. The proposed ADC fabricated in TSMCs 65-nm general-purpose process occupies an area of 0.0338 mm2 and consists of two time-interleaved channels, each operating at 110 MS/s. The sampling capacitor is separated from the capacitive DAC array by performing the input and DAC reference subtraction in the current domain rather than as done traditionally in the charge domain. This allows for an extremely small input capacitance of 133 fF. The measured ADC SFDR is 57 dB and the measured ENOB is 7.55 bits at Nyquist rate while using 1.55-mW power from a 1-V supply.

Inverter-Based Circuit Design Techniques for Low Supply Voltages

1 Introduction -- 2 Biasing -- 3 Inverter based OTA Design -- 4 ADC Driver -- 5 Current Mirror Based Filter -- 6 All MOSCAP Based Continuously Tunable Filter -- 7 ADC.

All MOSCAP Based Continuously Tunable Filter

This chapter presents an inverter based filter design that uses only MOSCAP as filter capacitors. Further in the design the load capacitance compensates the negative feedback network allowing the majority of current to flow into the load. This results in an increase in the overall power efficiency. As a proof of concept, a third order inverter based 34–314 MHz tunable continuous time channel select filter for software-defined radios is fabricated in TSMC’s 65 nm technology. By using the high density tunable MOSCAPs at a low swing node, the filter achieves an OIP3 of +25.24 dBm while drawing 4.2 mA from a 1.1 V supply and occupies an area of 0.007 mm2. The measured intermodulation distortion varies by 5 dB across a 120∘ variation in temperature and 6.5 dB across a 200 mV variation in power supply. Further, the filter presents a high impedance node at the input and a low impedance node at the output easing system integration.

Inverter Based OTA Design

The increased demand for battery operated devices has placed added pressure on lowered supply voltages. Technology scaling proportionally scales supply voltages to maintain device reliability but threshold voltages have not scaled as rapidly to limit the off current leakage in transistors. Delta sigma ADCs, particularly, continuous time delta sigma modulator are attractive due to implicit anti-aliasing, relaxed speed requirements on the active elements and the use of resistive input impedances. Although the use of multibit quantizers relaxes the design of the loop filter and are less sensitive to clock jitter, single-bit designs are simpler and do not require any dynamic element matching. The design of first integrator in a single bit modulator with adequate linearity and low power is always a challenge particularly in lower technologies [21].