Rakhi Narang

A Dielectric-Modulated Tunnel-FET-Based Biosensor for Label-Free Detection: Analytical Modeling Study and Sensitivity Analysis

In this paper, an analytical model for a p-n-p-n tunnel field-effect transistor (TFET) working as a biosensor for label-free biomolecule detection purposes is developed and verified with device simulation results. The model provides a generalized solution for the device electrostatics and electrical characteristics of the p-n-p-n-TFET-based sensor and also incorporates the two important properties possessed by a biomolecule, i.e., its dielectric constant and charge. Furthermore, the sensitivity of the TFET-based biosensor has been compared with that of a conventional FET-based counterpart in terms of threshold voltage (Vth) shift, variation in the on-current (Ion) level, and Ion/Ioff ratio. It has been shown that the TFET-based sensor shows a large deviation in the current level, and thus, change in Ion can also be considered as a suitable sensing parameter. Moreover, the impacts of device parameters (channel thickness and cavity length), process variability, and process-induced damage on the sensitivity of the biosensor have also been discussed.

Assessment of Ambipolar Behavior of a Tunnel FET and Influence of Structural Modifications

In the present work, comprehensive investigation of the ambipolar characteristics of two silicon (Si) tunnel field-effect transistor (TFET) architectures (i.e. p-i-n and p-n-p-n) has been carried out. The impact of architectural modifications such as heterogeneous gate (HG) dielectric, gate drain underlap (GDU) and asymmetric source/drain doping on the ambipolar behavior is quantified in terms of physical parameters proposed for ambipolarity characterization. Moreover, the impact on the miller capacitance is also taken into consideration since ambipolarity is directly related to reliable logic circuit operation and miller capacitance is related to circuit performance.

Dielectric Modulated Tunnel Field-Effect Transistor—A Biomolecule Sensor

In this letter, we propose a dielectric modulated double-gate tunnel field-effect transistor (DG-TFET)-based sensor for low power consumption label-free biomolecule detection applications. A nanogap-embedded FET-based biosensor has already been demonstrated experimentally, but a TFET-based biosensor has not been demonstrated earlier. Thus, a concept of TFET-based sensor is presented by analytical and simulation-based study. The results indicate better sensitivity toward two different effects (dielectric constant and charge of biomolecule) in comparison with a FET-based biosensor, and the additional advantages of CMOS compatibility, low leakage (low static power dissipation), and steep subthreshold slope make TFET an attractive alternative architecture for CMOS-based sensor applications.

Drain current model for a gate all around (GAA) p–n–p–n tunnel FET

Abstract A two dimensional drain current model has been proposed for a gate all around silicon p–n–p–n (pocket doped or tunnel source) tunnel field effect transistor (TFET) including the influence of drain voltage and source/drain depletion widths. The results extracted through numerical simulations have been used to obtain a semi empirical formulation of tunnel barrier width ( L BW ) which captures the dependence of gate voltage, drain voltage, and geometrical parameters (radii ( R ) and gate oxide thickness ( t ox )). The model is then used for evaluating various electrical parameters such as: drain current I ds , sub-threshold swing ( SS ), trans-conductance ( g m ), and device efficiency ( g m / I ds ). The impact of scaling R and t ox on the above mentioned parameters have also been investigated. Moreover, the model depicts the influence of pocket doping and pocket width (which are crucial parameters for optimization of p–n–p–n TFET performance) on the energy band profile of a p–n–p–n TFET very well. The modeled results are in good agreement with the device simulation results.

Impact of Temperature Variations on the Device and Circuit Performance of Tunnel FET: A Simulation Study

The paper presents a comprehensive comparison study of p-i-n and p-n-p-n tunnel field-effect transistor (TFET) architectures and the impact of temperature on their dc and circuit performance. The impact of a hetero-gate (HG) dielectric on the circuit performance also forms the part of the study. The device performance of p-i-n and p-n-p-n TFET with high-k dielectric and HG dielectric and the effect of temperature on the drain current characteristics, Ion/Ioff, and threshold voltage has been investigated and compared with MOSFET. Furthermore, the variations in the inverter (n-TFET with resistive load) transient characteristics and the fall delay due to temperature variations are studied using mixed mode simulations carried out with ATLAS device simulation software. Results reveal that TFET exhibits weak temperature dependence when the current conduction is band-to-band tunneling dominated, while the temperature dependence increases in the off-state regime, and the fall delay of resistive load n-TFET inverter decreases with increasing temperature.

Comparative Analysis of Dielectric-Modulated FET and TFET-Based Biosensor

An extensive study is presented to describe the impact of partial hybridization on the device electrostatics and on current of a silicon dielectric-modulated tunnel field effect transistor (DM-TFET). To gain insight into the various design considerations and factors influencing the sensitivity, both process-related issue such as cavity length variation and real-time issues related to biomolecules behavior such as partial hybridization, charge, and position of receptors/target molecules have been investigated through extensive numerical simulations. The results indicate that TFET-based sensor does not suffer from scaling issues and thus can help in miniaturization without compromising the sensitivity, unlike a nanogap-embedded DM-FET.

Device and Circuit Level Performance Comparison of Tunnel FET Architectures and Impact of Heterogeneous Gate Dielectric

This work presents a comparative study of four Double Gate tunnel FET (DG-TFET) architectures: conventional p-i-n DG-TFET, p-n-p-n DG-TFET, a gate dielectric engineered Heterogate (HG) p-i-n DG-TFET and a new device architecture with the merits of both Hetero Gate and p-n-p-n, i.e. HG p-n-p-n DG-TFET. It has been shown that, the problem of high gate capacitance along with low ON current for a p-i-n TFET, which severely hampers the circuit performance of TFET can be overcome by using a p-n-p-n TFET with a dielectric engineered Hetero-gate architecture (i.e. HG p-n-p-n). P-n-p-n architecture improves the ON current and the heterogeneous dielectric helps in reducing the gate capacitance and suppressing the ambipolar behavior. Moreover, the HG architecture does not degrade the output characteristics, unlike the gate drain underlap architecture, and effectively reduces the gate capacitance.

Modeling and TCAD Assessment for Gate Material and Gate Dielectric Engineered TFET Architectures: Circuit-Level Investigation for Digital Applications

This paper deals with the development of a generalized model describing the device electrostatic behavior of three different double gate n-type tunnel FET (TFET) architectures, i.e., dual material gate (DMG) TFET, heterodielectric (H-D) TFET, and dual material gate heterodielectric (DMG H-D). The model is advantageous in capturing the impact of dielectric and the metal gate length variation where a comparative study among these three aforementioned device architectures has been made in terms of various electrostatic parameters, such as surface potential, energy-band profile, and electric field, incorporating the impact of interface oxide charges. Subsequently, TCAD-based digital performance investigation for all these architectures has been performed where their capacitive behavior and the transient performance has been carefully analyzed and optimized by varying the metal work function (M1) and length (L1) value for both, i.e., the dielectric material and the metal gate. Both the modeling and simulation results reveal that the proposed architecture, i.e., DMG H-D TFET, outperforms the other two architectures, i.e., DMG and H-D TFET.

Simulation study for Dual Material Gate Hetero-Dielectric TFET: Static performance analysis for analog applications

This paper presents simulation study of Static characteristics for DMG (Dual Material Gate) Hetero-Dielectric (H-D) Tunnel FET. Here, two previously reported device architectures i.e. a DMG Single Dielectric TFET and SMG (Single Material Gate) Hetero-Dielectric TFET have been optimized by tuning the work functions and length and later on their combined impact on the proposed device architecture i.e. DMG Hetero-Dielectric Tunnel FET (DMG H-D TFET) is been studied. Electrical parameters such as threshold voltage, drain current I_ds, Sub threshold Slope, I_on to I_off ratio, ambipolar current I_amb have been studied. Some of the important analog parameters like transconductance g_m, drain conductance g_d, Output resistance R_out, transconductance generation efficiency g_m/I_ds have also been studied using ATLAS Device Simulation Software.

Modeling and simulation of multi layer gate dielectric double gate tunnel field-effect transistor (DG-TFET)

This work presents a study on Double gate Tunnel Field effect transistor (DG-TFET) with a multi layer gate dielectric, commonly known as Gate Stack (GS) architecture. An analytical model has been developed to obtain compact analytical expressions for various parameters like electron concentration in the channel, energy bands, potential and electric field at the tunneling junction. Band to band tunneling generation rate and tunneling probability has been evaluated. The performance of gate stack DG-TFET in terms of high drive current is shown through device simulation. The results obtained from analytical expressions are compared with device simulator results.