R. S. Gupta

Physics-based analytical modeling of potential and electrical field distribution in dual material gate (DMG)-MOSFET for improved hot electron effect and carrier transport efficiency

We propose a new two-dimensional (2-D) analytical model of a dual material gate MOSFET (DMG-MOSFET) for reduced drain-induced barrier lowering (DIBL) effect, merging two metal gates of different materials, laterally into one. The arrangement is such that the work function of the gate metal near the source is higher than the one near the drain. The model so developed predicts a step-function in the potential along the channel, which ensures screening of the drain potential variation by the gate near the drain. The small difference of voltage due to different gate material keeps a uniform electric field along the channel, which in turn improves the carrier transport efficiency. The ratio of two metal gate lengths can be optimized along with the metal work functions and oxide thickness for reducing the hot electron effect. The model is verified by comparison to the simulated results using a 2-D device simulator ATLAS over a wide range of device parameters and bias conditions.

Modeling and simulation of a nanoscale three-region tri-material gate stack (TRIMGAS) MOSFET for improved carrier transport efficiency and reduced hot-electron effects

Two-dimensional (2-D) analytical modeling for a novel multiple region MOSFET device architecture-Tri-Material Gate Stack MOSFET-is presented, which shows reduced short-channel effects at short gate lengths. Using a three-region analysis in the horizontal direction and a universal depletion width boundary condition, the 2-D potential and electric field distribution in the channel region along with the threshold voltage of the device are obtained. The proposed model is capable of modeling electrical characteristics like surface potential, electric field, and threshold voltage of various other existent MOSFET structures like dual-material-gate, electrically induced shallow junction/straddle-gate (side-gate), and single-material-gate MOSFETs, with and without the gate stack architecture. The 2-D device simulator ATLAS is used over a wide range of parameters and bias conditions to validate the analytical results

TCAD Assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and Its Multilayered Gate Architecture—Part I: Hot-Carrier-Reliability Evaluation

This paper discusses a hot-carrier-reliability assessment, using ATLAS device simulation software, of a gate electrode workfunction engineered recessed channel (GEWE-RC) MOSFET involving an RC and GEWE design integrated onto a conventional MOSFET. Furthermore, the impact of gate stack architecture and structural design parameters, such as gate length, negative junction depth, substrate doping (NA), gate metal workfunction, substrate bias, drain bias, and gate oxide permittivity on the device behavior of GEWE-RC MOSFET, is studied in terms of its hot-carrier behavior in Part I. Part II focuses on the analog performance and large signal performance metrics evaluation in terms of linearity metrics, intermodulation distortion, device efficiency and speed-to-power dissipation design parameters, and the impact of gate stack architecture and structural design parameters on the device reliability. TCAD simulations in Part I reveal the reduction in hot-carrier-reliability metrics such as conduction band offset, electron velocity, electron temperature, hot-electron-injected gate current, and impact-ionization substrate current. This paper thus optimizes and predicts the feasibility of a novel design, i.e., GEWE-RC MOSFET for high-performance applications where device and hot-carrier reliability is a major concern.

Drain current model for a gate all around (GAA) p–n–p–n tunnel FET

Abstract A two dimensional drain current model has been proposed for a gate all around silicon p–n–p–n (pocket doped or tunnel source) tunnel field effect transistor (TFET) including the influence of drain voltage and source/drain depletion widths. The results extracted through numerical simulations have been used to obtain a semi empirical formulation of tunnel barrier width ( L BW ) which captures the dependence of gate voltage, drain voltage, and geometrical parameters (radii ( R ) and gate oxide thickness ( t ox )). The model is then used for evaluating various electrical parameters such as: drain current I ds , sub-threshold swing ( SS ), trans-conductance ( g m ), and device efficiency ( g m / I ds ). The impact of scaling R and t ox on the above mentioned parameters have also been investigated. Moreover, the model depicts the influence of pocket doping and pocket width (which are crucial parameters for optimization of p–n–p–n TFET performance) on the energy band profile of a p–n–p–n TFET very well. The modeled results are in good agreement with the device simulation results.

Modeling and simulation of asymmetric gate stack (ASYMGAS)-MOSFET

Abstract We propose a new structure, asymmetric gate stack (ASYMGAS)-MOSFET and its 2-D analytical model. There is two-layer gate stack oxide near the drain and single gate oxide near the source. The model predicts a step function profile in the potential along the channel, which ensures reduced DIBL. In ASYMGAS-MOSFET, the average electric field in the channel is enhanced, and therefore electron velocity, near the source, which improves the overall carrier transport efficiency. The results so obtained are verified using a two-dimensional device simulator, ATLAS, over a wide range of device parameters and bias conditions. Good agreement is obtained for channel lengths down to 0.15 μm. Thus, confirming the validity of our model.

Threshold voltage model for small geometry AlGaN/GaN HEMTs based on analytical solution of 3-D Poisson's equation

A simple and accurate analytical model for the threshold voltage of AlGaN/GaN high electron mobility transistor (HEMT) is developed by solving three-dimensional (3-D) Poisson equation to investigate the short channel effects (SCEs) and the narrow width effects present simultaneously in a small geometry device. It has been demonstrated that the proposed model correctly predicts the potential and electric field distribution along the channel. In the proposed model, the effect of important parameters such as the thickness of the barrier layer and its doping on the threshold voltage has also been included. The model is, further, extended to find an expression for the threshold voltage in the sub-micrometer regime. The accuracy of the proposed analytical model is verified by comparing the model results with 3-D device simulations for different gate lengths and widths.

Two-dimensional analytical threshold voltage model for DMG Epi-MOSFET

A two-dimensional (2-D) analytical model of a dual material gate (DMG) epitaxial (Epi)-MOSFET for improved, SCEs, hot electron effects, and carrier transport efficiency is presented. Using a two-region polynomial potential distribution and a universal boundary condition, we calculated the 2-D potential and electric field distribution along the channel. An expression for threshold voltage for short-channel DMG Epi-MOSFETs is also derived. The ratio of gate lengths has been varied to show which gate length ratio gives the best performance. The analytical results have been validated by the 2-D device simulator ATLAS over a wide range of device parameters and bias conditions.

Dual Material Double-Layer Gate Stack SON MOSFET: A Novel Architecture for Enhanced Analog Performance—Part I: Impact of Gate Metal Workfunction Engineering

In this paper, we present a simulation study, using ATLAS-2D, of analog circuit performance metrics for the dual-material gate (DMG) MOSFETs in Part I. Part II focuses on the impact of double-layer gate stack architecture on the analog performance and fT-gain relationship of the silicon-on-nothing MOSFETs with and without DMG. The simulation results in Part I demonstrate that, out of the several combinations in DMG MOSFET design studied, the DMG device with an LM1/L ratio of frac12 amalgamates the advantages of using a high metal workfunction gate M1 and a low metal workfunction gate M2 in the most efficient manner. An increase in early voltage and a reduced output conductance from the DMG MOSFET design are the driving forces for the observed performance improvement.

Dual-Material Double-Layer Gate Stack SON MOSFET: A Novel Architecture for Enhanced Analog Performance—Part II: Impact of Gate-Dielectric Material Engineering

Part I of this paper dealt with the simulation study, using ATLAS 2D, of analog-circuit performance metrics for the dual-material-gate (DMG) silicon-on-nothing (SON) MOSFET. It was reported that, out of the several combinations in the DMG design studied, the DMG device with LM1/ L ratio as 1/2 amalgamates the advantages of using a high metal work-function gate M1 and low metal work-function gate M2 in the most efficient manner. This paper focuses upon the effect of double-layer gate stack (DGS) (high-k/SiO2) on the single-material-gate (SMG) SON and the DMG SON MOSFETs. Improved Early voltage and reduced output conductance of the DMG SON MOSFETs are the driving forces behind the observed increase in intrinsic gain and fT-gain relationship for the DMG devices over SMG SON MOSFETs, with the DMG SON MOSFETs having LM1/L ratio as 1/2, proving to be the best choice among various LM1/L ratios studied. A further improvement in intrinsic gain in DMG DGS SON MOSFETs comes about because of increased gate control on the channel, thus establishing design guidelines aiming at higher gain and better fT-gain relationship.

Hot-Carrier Reliability and Analog Performance Investigation of DMG-ISEGaS MOSFET

Dual-material-gate (DMG) insulated shallow extension gate-stack MOSFET involving dielectric pocket (DP) and DMG assimilation onto the conventional MOSFET has been studied. Simulations reveal a reduction in substrate leakage current, linearity improvement, enhancement in - g_m/I_DS, early voltage (V_EA), and g_m/g_d, down to 50-nm gate length as an outcome of this DP and DMG integration.