Ralf Arnold

On-chip evaluation, compensation and storage of scan diagnosis data

Technology and product ramp-up suffers increasingly from systematic production defects. Diagnosis of scan-test fail data plays an important role in yield enhancement, as diagnosis of scan fail data helps to understand and overcome systematic production defects. Acquisition of scan fail data during high-volume production may lead to significant test time overhead. A new on-chip architecture is presented that evaluates scan-test results and stores relevant scan diagnostic information on chip. Scan diagnostic data is unloaded for offline analysis after the scan test has been finished. Unloading scan diagnostic data from chip requires only very little test time overhead. Moreover, the proposed technique is automatic test equipment independent and accelerates test program development. A detailed implementation example, based on a state-of-the-art SoC device, is given.

On-Chip Evaluation, Compensation, and Storage of Scan Diagnosis Data - A Test Time Efficient Scan Diagnosis Architecture

Technology and product ramp up suffers increasingly from systematic production defects. Diagnosis of scan test fail data plays an important role in yield enhancement as diagnosis of scan fail data helps to understand and overcome systematic production defects. Acquisition of scan fail data during high-volume production can lead to significant test time overhead. This paper presents a new on-chip architecture that evaluates scan test results and stores relevant scan diagnosis information on chip. Scan diagnosis data can be accessed after the scan test has finished with very little test time overhead. Moreover, the proposed technique is ATE independent. An implementation example, based on a state-of-the-art SoC device, is reported

Cell-aware experiences in a high-quality automotive test suite

High quality is an absolute necessity for automotive designs. This paper describes an approach to improve the overall defect coverage for CMOS-based high quality automotive designs. We present results from a cell-aware (CA) characterization flow for 216 cells, the pattern generation flow for a 130nm smart power design, and high-volume production test results achieved after testing multimillion parts. The idea behind CA tests is to detect cell-internal (CI) bridges, opens, leaking and high resistive transistor defects which are undetected with state-of-the-art tests. The production test results have shown that the CA tests detect various failing parts during a first wafer sort test which still resulted into unique failing parts after a second wafer sort test done at a different temperature and with additional tests. The obtained results encouraged us to continue this work beyond this paper to run further experiments with the final goal to eliminate the stuck-at (SA) and transition delay (TR) test by simultaneously improving the quality with CA tests which are a superset of SA and TR tests.

Deterministic IDDQ diagnosis using a net activation based model

In Automotive business, the quiescent supply current test (IDDQ) is a widely used and valuable test method to screen out production failures and reach the required low defective parts per million (DPPM) quality targets. Automatic Test Pattern Generation (ATPG) tools can generate scan based IDDQ patterns with high test coverage for Pseudo Stuck-At (PSA) faults. Functional pass but IDDQ failing devices need to be diagnosed for various purposes. In this paper a fast simulation based method is proposed to diagnose IDDQ failures with single or multiple defects for digital circuitry. The results are verified on real silicon for several 130nm Automotive designs. Furthermore automation of the diagnosis method for high volume diagnosis similar to scan volume diagnosis is shown in the paper outlook.