Hans-Dieter Oberle

Enhanced fault modeling for DRAM test and analysis

For typical physical DRAM cell array defects, logical fault models are derived. These models completely and unambiguously describe all coupling faults and pattern sensitivities. Thus, test patterns are developed for production tests and fault analyses with high fault coverage.<<ETX>>

Test Pattern Development and Evaluation for DRAMs with Fault Simulator RAMSIM

A fault simulator for DRAMS has been devel- oped to determine the fault coverage of test patterns . The realistic fault models are derived from DRAM fail- ure analysis and include complex pattern sensitivity mechanisms.