Ralph Hasholzner

A very fast and quasi-accurate power-state-based system-level power modeling methodology

In this paper, we propose a novel system-level power modeling methodology that allows for very fast joint power-performance evaluation at specification phase. This methodology adopts approximately-timed task-accurate performance models and augments them with power-state-based power models to enable efficient simulation. A flexible method is also proposed to model complex dynamic power management policies so that their effects can be evaluated. We validate the accuracy of our methodology by comparing simulation results with measurements on a real mobile phone platform. Experimental results show that the simulated power profile matches very well with the measurements and it only takes about 100 ms to simulate a 20 ms GSM paging burst use case.

The effects of phase noise on 26 Mb/s OFDMA broadband radio in the local loop systems

The effects of phase noise on broadband radio in the local loop (BRITL) systems employing orthogonal frequency division multiple access (OFDMA) are assessed analytically and numerically. Phase noise causes a common phase error (CPE) and inter-carrier interferences (ICI). The former is easy to estimate and equalize, since it identically affects all subcarriers. It is shown that neither a significant degradation of the symbol error rate (SER) due to CPE nor a detrimental error floor due to ICI is introduced provided the constant range of the phase noise power spectral density (PSD) of the stabilized oscillator does not exceed 20 kHz. Above that limit, the SER performance is dominated by a prohibitive error floor caused by ICI.

End-to-end power estimation for heterogeneous cellular LTE SoCs in early design phases

System-level power modeling and estimation is a non-trivial task for the architecture and power management strategies exploration during early design phases of a cellular LTE modem. It requires system architects to consider not only highly heterogeneous SoC architectures, but also various worldwide LTE network configurations and dynamic scheduling which impact modem power consumption significantly. In this work, we present an LTE end-to-end power model to enable a fast power consumption evaluation of different LTE modem system architecture options. The power model for digital elements is based on power states and refined by execution phases. For analogue/RF elements, the model is differentiated by each operational state consuming a constant power. The LTE power amplifier, as a major power contributor, is modeled at a detailed abstraction level using piece-wise polynomial equations with the consideration of band-to-band variations and the envelope tracking operation. Using this heterogeneous power modeling approach, different system design choices can be compared and explored holistically at a rather low modeling effort and a fast simulation speed. Moreover, the power estimation of the LTE modem takes into account the impact of real-life networks, which enables the easy adaptation to various network scenarios in early design phases. Thanks to this configurable end-to-end model, the productivity of a power modeling team can be improved by 10× to meet the challenge of increased exploration space in LTE modem concept design under tight time-to-market requirements.

MAESTRO— Holistic Actor-Oriented Modeling of Nonfunctional Properties and Firmware Behavior for MPSoCs

Modeling and evaluating nonfunctional properties such as performance, power, and reliability of embedded systems are tasks of utmost importance. In this article, we introduce MAESTRO, a methodology for the modeling and evaluation of nonfunctional properties and embedded firmware of MPSoC architecture components at the Electronic System Level (ESL). In contrast to existing design flows that provide predefined performance models, MAESTRO defines a flexible approach that allows to define virtual prototypes that can be easily customized and extended to evaluate multiple nonfunctional properties of interest at different levels of abstraction. In MAESTRO, a design is composed purely from actor-oriented models. This enables typical ESL features such as automatic design space exploration and synthesizability of HW and SW components, typically missing in very general design flows. Unique to MAESTRO is the separation and coordination of the interaction between application functionality, firmware, and performance models for the evaluation of nonfunctional properties, and their complex interactions within a single Model-of-Computation (MoC). The main advantages of MAESTRO are: (I) Extensible modeling of interdependent nonfunctional properties of heterogeneous MPSoC components; (II) high flexibility to investigate the appropriate trade-off between modeling effort and accuracy of nonfunctional property evaluators; (III) a holistic approach for modeling application functionality as well as firmware affecting the evaluation of nonfunctional properties. Regarding (II), we present a mobile baseband processor platform use-case, executing a GSM paging application. To demonstrate (I) and (III), we present the modeling of a complex ESL processor virtual prototype, running a soft real-time application and equipped with both a power and reliability manager.

On robust task-accurate performance estimation

Task-accurate performance estimation methods are widely applied in early design phases to explore different architecture options. These methods rely on accurate annotations generated by software profiling or real measurements to guarantee accurate results. However, in practice, such accurate annotations are not available in early design phases due to lack of source code and hardware platform. Instead, estimated mean or worstcase annotations are usually used, which makes the final result inaccurate because of the errors induced by the estimations, especially for designs with tight time constraints. In this paper, we propose a novel methodology that combines Distributionally Robust Monte Carlo Simulation with task-accurate performance estimation method to guarantee robust system performance estimation in early design phases, i.e., determining the lower bound of the confidence level of fulfilling a specific time constraint. Instead of using accurate annotations, our method only uses estimated annotations in the form of intervals and it does not make any assumptions of the distribution types of these intervals.

A state-based power estimation methodology at system level for integrated RF front-ends

This paper introduces an approach to model the power consumption of analog and mixed-signal systems at system level. The method is based on power state machines and is practically applied to a zero-IF receiver. The power state machines model the static power consumption of components with respect to their current state or state transition. The power consumption per state and state transition, respectively, is obtained from a low-level circuit simulation or from measurement. The concept of power state machines can be used for any analog component and enables the simulation of heterogeneous systems with the benefit of a fast simulation time.

A Binary Time Series Model of LTE Scheduling for Machine Learning Prediction

In todays Third-Generation Partnership Project (3GPP) Long-Term Evolution Advanced (LTE-A) cellular radio networks, battery lifetime is critical for mobile devices. During time intervals of no user data transmit or receive activity, energy for receiving and processing irrelevant control information in a mobile device could be saved. Therefore, we propose a binary time series model at 1 ms transmission time interval (TTI) granularity to predict the control channel information. To assess the predictability of the proposed time series, we apply three well-known machine learning (ML) algorithms combined with a non-intrusive cost-sensitive classification (CSC) scheme. Predictions of the proposed time series model successfully reach false negative rates (FNRs) below 2%.

Variation-aware leakage power model extraction for system-level hierarchical power analysis

System-level power analysis is commonly used in modern SoC design processes to evaluate power consumption at early design phases. With the increasing variations in manufacturing, the statistical characteristics of parameters are also incorporated in the state-of-the-art methods. However, the spatial correlation between modules still remains as a challenge for system-level statistical power analysis where power models generated from individual modules are used for analysis efficiency or IP protection. In this paper, we propose a novel method to extract variation-aware and correlation-inclusive leakage power models for fast and accurate system-level analysis. For each individual module we generate a power model with different correlation information specified by the module vendor or customer. The local random variables in the power models are replaced by the corresponding ones at system level to reconstruct the correlation between modules so that the accuracy of system-level analysis is guaranteed. Experimental results show that our method are very accurate while being 1000X faster than Monte Carlo simulation and 70X-100X faster than the flattened full chip statistical leakage analysis.

The effects of multiple access schemes on equalization for broadband wireless local loop systems

Single carrier time division multiple access (TDMA) and orthogonal frequency division multiple access (OFDMA) are promising for broadband fixed radio access (FRA) in terms of flexibility, bandwidth-efficiency and implementation cost. Coherent detection of QPSK-symbols requires adaptive equalization. We focus on equalizer adaptation in time-variant frequency-selective FRA-channels in the presence of oscillator phase noise. The implementation complexity of the equalizer is estimated as well.

Exploiting Predictability in Dynamic Network Communication for Power-Efficient Data Transmission in LTE Radio Systems

In embedded systems powered by batteries, power is undoubtedly a critical resource making power management an important topic in the design phase. Even though power management is a heavily researched topic, most approaches focus on improving the way the power manager reacts to outside control events. In this paper, we propose techniques that not only react but rather try to predict these outside control events in advance, thus, broadening the capabilities of any employed power manager by allowing for superior transition decisions and even saving redundant calculations. We present results on employing a predictive power management system that couples a classic dynamic power manager with a machine learning subsystem in the context of a mobile device in a Long Term Evolution (LTE) system, with emphasis on evaluating the potential of saving power as well as the handling of the induced prediction uncertainty. First, we examine the LTE communication protocol and showcase certain control data that has to be received periodically, but may contain no information for the receiver. Finally, we show a proof-of-concept based on real LTE traces and hardware simulation, that prediction of this information can be leveraged to allow for a far superior decision process compared to a non-predicting system. Here, we achieve a theoretical best case power saving of 15 % for an idealized prediction with 100 % accuracy and no additional power consumption.