Ram Peltinov

Phenomenology of electron-beam induced photoresist shrinkage trends

For many years, lithographic resolution has been the main obstacle in keeping the pace of transistor densification to meet Moores Law. For the 45 nm node and beyond, new lithography techniques are being considered, including immersion ArF (iArF) lithography and extreme ultraviolet lithography (EUVL). As in the past, these techniques will use new types of photoresists with the capability to print 45 nm node (and beyond) feature widths and pitches. In a previous paper [1], we focused on ArF and iArF photoresist shrinkage. We evaluated the magnitude of shrinkage for both R&D and mature resists as a function of chemical formulation, lithographic sensitivity, scanning electron microscope (SEM) beam condition, and feature size. Shrinkage results were determined by the well accepted methodology described in ISMIs CD-SEM Unified Specification [2]. A model for resist shrinkage, while derived elsewhere [3], was presented, that can be used to curve-fit to the shrinkage data resulting from multiple repeated measurements of resist features. Parameters in the curve-fit allow for metrics quantifying total shrinkage, shrinkage rate, and initial critical dimension (CD) from before e-beam exposure. The ability to know this original CD is the most desirable result; in this work, the ability to use extrapolation to solve for a given original CD value was also experimentally validated by CD-atomic force microscope (AFM) reference metrology. Historically, many different conflicting shrinkage results have been obtained among the many works generated through the litho-metrology community. This work, backed up by an exhaustive dataset, will present an explanation that makes sense of these apparent discrepancies. Past models for resist shrinkage inherently assumed that the photoresist line is wider than the region of the photoresist to be shrunk [3], or, in other words, the e-beam never penetrates enough to reach all material in the interior of a feature; consequently, not all photoresist is affected by the shrinkage process. In actuality, there are two shrinkage regimes, which are dependent on resist feature CD or thickness. Past shrinkage models are true for larger features. However, our results show that when linewidth becomes less than the eventual penetration depth of the e-beam after full shrinkage, the apparent shrinkage magnitude decreases while shrinkage speed accelerates. Thus, for small features, most shrinkage occurs within the first measurement. This is crucial when considering the small features to be fabricated by immersion lithography. In this work, the results from the previous paper [1] will be shown to be consistent with numerically simulated results, thus lending credibility to the postulations in [1]. With these findings, we can conclude with observations about the readiness of SEM metrology for the challenges of both dry and immersion ArF lithographies as well as estimate the errors involved in calculating the original CD from the shrinkage trend.

Accurate in-resolution level overlay metrology for multipatterning lithography techniques

Multi patterning lithography (MPL) breaks the k1=0.25 barrier to become the main candidate for 32nm device fabrication before 2010. When using MPL, overlay (OVL) becomes an essential part of the overall critical dimension (CD) budget and therefore can no longer be treated as a separate process control measure. Furthermore, the CD measured at each of the two consecutive lithography steps must be combined into one single 32nm process control measure and will require further improvements of CD-SEM precision, resolution and accuracy. The metrology challenges involved in measuring double patterning CD and OVL arise from the fact that across chip pitch variations (ACPV) are determined by the two separate lithographic processes [1]. This aspect makes the control of the process significantly more complex and requires careful measurement of the processes, both individually as well as combined. Meeting the ITRS specifications for CD and localized OVL measurements beyond 32nm half pitch is challenging and will require innovative CDSEM algorithmic solutions. This paper is a follow-up from last years paper that introduced SEM metrology for MPL technology. In this paper, we report on the actual implementation of combined CD and OVL metrology solutions for the latest immersion scanner generation. We will describe the latest OVL measurements performed at ASML and demonstrate the robustness of the novel algorithm for accurate separation and recombination of two individual CD populations related to the consecutive MPL steps.

SEM metrology for advanced lithographies

For many years, lithographic resolution has been the main obstacle for keeping the pace of transistor densification to meet Moores Law. The industry standard lithographic wavelength has evolved many times, from G-line to I-line, deep ultraviolet (DUV) based on KrF, and 193nm based on ArF. At each of these steps, new photoresist materials have been used. For the 45nm node and beyond, new lithography techniques are being considered, including immersion ArF lithography and extreme ultraviolet (EUV) lithography. As in the past, these techniques will use new types of photoresists with the capability of printing 45nm node (and beyond) feature widths and pitches. This paper will show results of an evaluation of the critical dimension-scanning electron microscopy (CD-SEM)-based metrology capabilities and limitations for the 193nm immersion and EUV lithography techniques that are suggested in the International Technology Roadmap for Semiconductors. In this study, we will print wafers with these emerging technologies and evaluate the performance of SEM-based metrology on these features. We will conclude with preliminary findings on the readiness of SEM metrology for these new challenges.

SEM-contour based mask modeling

With the push toward the 32nm node, OPC modeling must respond in kind with additional accuracy enhancements. One area of lithographic modeling that has basically gone unchecked is mask fidelity. Mask linearity is typically built into the OPC model since the calibration data contain this information, but mask pattern fidelity is almost impossible to quantify for OPC modeling. Mask fidelity is the rounding and smoothing of the mask features relative to the post-OPC layout intent, and there is no robust metric available to quantify these effects. With the introduction of contour-based model calibration, mask fidelity modeling is possible. This work evaluates techniques to quantify mask modeling and methods to gauge the accuracy improvement that mask fidelity modeling would project into the lithographic process using contour-based mask model calibration.

Metrology challenges for advanced lithography techniques

Traditionally CD SEM has been positioned as a local critical dimension measurement and analysis technique. Emerging lithography techniques introduce new challenges for CD SEM such as overlay error measurements. For the sub 45 nm technology nodes, several new lithography approaches are developed that rely on multiple lithography and deposition and etch process steps. Seamless integration of these lithography and deposition and etch process steps requires specific CD and/or overlay metrology capability for optimal CD and overlay registration performance. Areas of development are focused on CD measurement algorithms and correlation after resist develop and subsequent etch steps. These new lithography processes require unprecedented accuracy and overlay resolution. Fundamental and application specific metrology challenges and solutions will be highlighted. In addition, this paper will report on unique overlay target design in combination with innovative CD SEM measurement techniques to meet those challenges.

Transistor layout configuration effect on actual gate LER

The importance of Line Edge Roughness (LER) and Line Width Roughness (LWR) has long surpassed its effect on process control. As devices scale down, the roughness effects have become a major hindrance for further advancement along Moores law. Many studies have been conducted over the years on the sensitivity of LER to various changes in the materials and the process, which have been considered the main way to tackle the problem - especially through Photoresist improvement. However, despite the increased development of DFM tools in recent years, limited research was done as to LER sensitivity to layout, and the research that was done was limited to proximity effects. In this paper, we study the sensitivity of LER to the layout around the transistor, defined by the gate structure of poly over AA (Active Area). Using different types and geometries of transistors, we found that the poly-gate LER is sensitive to the structure of the Active Area around it (source/drain from gate to contact, both shape and length). Using local LER measurement (moving standard deviation of poly edge location), we found a clear correlation between LER value and the length of the AA/STI boundary located at a close range. Longer AA edges yield higher LER, as proved by comparing gate LER of dog-bone transistor with classical transistor. Based on these results, we suggest that LER is sensitive not only to proximity effects, but also to the layout of underlying layers, through the effect of light scattering of the edges during the lithographic process.

Metrology characterization for self-aligned double patterning

Self-Aligned Double Patterning (SADP) scheme is considered as one of the most promising lithographic techniques to meet the challenges for aggressive flash 32 nm semiconductor technology node and beyond. Monitoring the SADP stages implies the necessity to use metrology methods that meet advanced technology nodes requirements. One important growing metrology factor is the Line Edge Roughness (LER). This factor is most relevant due to the unique processing of the outer vs. inner edges in the SADP process. The aim of the present study is to evaluate the right metrics to tightly monitor SADP process, including the roughness behavior of the features on SADP layers, and seek correspondence of LER characteristics between SADP sequential process stages. Additional element of this study will be to examine the performance of CD-SEM roughness analysis on small features, with the usage of improved LER measurement method that takes into account the contribution of SEM imaging noise to the obtained LER values.

MacroCD contact ellipticity measurement for lithography tool qualification

Contact hole integrity is an important metric for IC manufacturers, which is reflected in tight ellipticity control as part of the lithography tool qualifications. The current ellipticity measurement methodology is very sensitive to random process variations of the contact hole shape. Determining ellipticity in a systematic manner poses a challenge on qualification productivity, as acquiring more data for statistical validity leads to unacceptably long measurement times. The introduction of the so-called MacroCD Vector measurement enables a single shot large sampling of contact holes, including vector calculation and averaging of all individual contact ellipticity results within the MacroCD measurement array. Based on these enhanced measurement features, it is shown that contact hole ellipticity can be determined with much higher accuracy while local, mostly process induced variations can be characterized simultaneously. This opens possibilities to study correlation between ellipticity and possible root causes in the litho process module.

CD-SEM application for generic analysis of two-dimensional features on wafers and reticles

SEM Metrology becomes the standard metrology for the mask industry, as the precision and accuracy requirements tighten continuously. At the same time, analysis of general shape features becomes an important task in wafer metrology. In this paper we consider the basic requirements and suggested implementations for performing 2D metrology on reticles and wafers, [i.e. measurements of OPC (Optical Proximity Correction) structures, End of Lines, Dual Damascene and Corner Rounding]. The authors consider the following challenges related to the development of a generic algorithm for general shape 2D analysis: (1) A generic segmentation of the feature. It should be robust to noise, as well as brightness and contrast changes. (2) The complexity of two dimensional general shape features metrology. Standard CD SEM metrology is based on metrics describing simple geometric shapes such as ellipses and lines). (3) Obtaining such metrics that can be used as handles for process control (i.e. what to measure on the 2D feature). In the first part of the paper we describe a novel algorithm for segmentation and geometric analysis of general shape features based on a Smoothing Spline and the methods of differential geometry. Next, we consider the numerical methods implemented for shape analysis of noisy contours. In the second part of the paper the performance of our methods on synthetic contours of circular arc with different noise levels is demonstrated. We conclude with sample results of several suggested metrics measured on real SEM images of reticles and wafers.

New approach for mapping and monitoring damascene trench depth using CD-SEM tilt imaging

Due to miniaturization of semiconductor devices, ArF (193nm) lithography is likely expected to be used for sub 100nm regime. For sub 100nm devices, high NA exposure tools and various strong off-axis illumination (OAI) conditions should be used. But unlike KrF (248nm) lithography, resist pattern collapse becomes one of the most serious problems in ArF lithography. In order to solve pattern collapse problem, thin resist process is generally introduced but its poor etch resistance is an obstacle for being applied in real production process. Due to this reason, new kinds of organic BARC materials are investigated and optimized to avoid pattern collapse. As mentioned, the most important issue in ArF organic BARC is believed to be the pattern collapse problem. A number of organic BARCs were made by varying polymer, cross-linker, thermal acid generator, and additive. We tried to analyze the key factor in terms of pattern collapse. This paper is to compare the various elements of the organic BARC formulation and to discuss what brings and causes pattern collapse.