Ofer Adan

Phenomenology of electron-beam induced photoresist shrinkage trends

For many years, lithographic resolution has been the main obstacle in keeping the pace of transistor densification to meet Moores Law. For the 45 nm node and beyond, new lithography techniques are being considered, including immersion ArF (iArF) lithography and extreme ultraviolet lithography (EUVL). As in the past, these techniques will use new types of photoresists with the capability to print 45 nm node (and beyond) feature widths and pitches. In a previous paper [1], we focused on ArF and iArF photoresist shrinkage. We evaluated the magnitude of shrinkage for both R&D and mature resists as a function of chemical formulation, lithographic sensitivity, scanning electron microscope (SEM) beam condition, and feature size. Shrinkage results were determined by the well accepted methodology described in ISMIs CD-SEM Unified Specification [2]. A model for resist shrinkage, while derived elsewhere [3], was presented, that can be used to curve-fit to the shrinkage data resulting from multiple repeated measurements of resist features. Parameters in the curve-fit allow for metrics quantifying total shrinkage, shrinkage rate, and initial critical dimension (CD) from before e-beam exposure. The ability to know this original CD is the most desirable result; in this work, the ability to use extrapolation to solve for a given original CD value was also experimentally validated by CD-atomic force microscope (AFM) reference metrology. Historically, many different conflicting shrinkage results have been obtained among the many works generated through the litho-metrology community. This work, backed up by an exhaustive dataset, will present an explanation that makes sense of these apparent discrepancies. Past models for resist shrinkage inherently assumed that the photoresist line is wider than the region of the photoresist to be shrunk [3], or, in other words, the e-beam never penetrates enough to reach all material in the interior of a feature; consequently, not all photoresist is affected by the shrinkage process. In actuality, there are two shrinkage regimes, which are dependent on resist feature CD or thickness. Past shrinkage models are true for larger features. However, our results show that when linewidth becomes less than the eventual penetration depth of the e-beam after full shrinkage, the apparent shrinkage magnitude decreases while shrinkage speed accelerates. Thus, for small features, most shrinkage occurs within the first measurement. This is crucial when considering the small features to be fabricated by immersion lithography. In this work, the results from the previous paper [1] will be shown to be consistent with numerically simulated results, thus lending credibility to the postulations in [1]. With these findings, we can conclude with observations about the readiness of SEM metrology for the challenges of both dry and immersion ArF lithographies as well as estimate the errors involved in calculating the original CD from the shrinkage trend.

Accurate in-resolution level overlay metrology for multipatterning lithography techniques

Multi patterning lithography (MPL) breaks the k1=0.25 barrier to become the main candidate for 32nm device fabrication before 2010. When using MPL, overlay (OVL) becomes an essential part of the overall critical dimension (CD) budget and therefore can no longer be treated as a separate process control measure. Furthermore, the CD measured at each of the two consecutive lithography steps must be combined into one single 32nm process control measure and will require further improvements of CD-SEM precision, resolution and accuracy. The metrology challenges involved in measuring double patterning CD and OVL arise from the fact that across chip pitch variations (ACPV) are determined by the two separate lithographic processes [1]. This aspect makes the control of the process significantly more complex and requires careful measurement of the processes, both individually as well as combined. Meeting the ITRS specifications for CD and localized OVL measurements beyond 32nm half pitch is challenging and will require innovative CDSEM algorithmic solutions. This paper is a follow-up from last years paper that introduced SEM metrology for MPL technology. In this paper, we report on the actual implementation of combined CD and OVL metrology solutions for the latest immersion scanner generation. We will describe the latest OVL measurements performed at ASML and demonstrate the robustness of the novel algorithm for accurate separation and recombination of two individual CD populations related to the consecutive MPL steps.

SEM metrology for advanced lithographies

For many years, lithographic resolution has been the main obstacle for keeping the pace of transistor densification to meet Moores Law. The industry standard lithographic wavelength has evolved many times, from G-line to I-line, deep ultraviolet (DUV) based on KrF, and 193nm based on ArF. At each of these steps, new photoresist materials have been used. For the 45nm node and beyond, new lithography techniques are being considered, including immersion ArF lithography and extreme ultraviolet (EUV) lithography. As in the past, these techniques will use new types of photoresists with the capability of printing 45nm node (and beyond) feature widths and pitches. This paper will show results of an evaluation of the critical dimension-scanning electron microscopy (CD-SEM)-based metrology capabilities and limitations for the 193nm immersion and EUV lithography techniques that are suggested in the International Technology Roadmap for Semiconductors. In this study, we will print wafers with these emerging technologies and evaluate the performance of SEM-based metrology on these features. We will conclude with preliminary findings on the readiness of SEM metrology for these new challenges.

Material contrast based inline metrology: process verification and control using back scattered electron imaging on CD-SEM

The Critical Dimension Scanning Electron Microscope (CDSEM) is the traditional workhorse solution for inline process control. Measurements are extracted from top-down images based on secondary electron collection while scanning the specimen. Secondary electrons holding majority of detection yield. These images provide more on the structural information of the specimen surface and less in terms of material contrast. In some cases there is too much structural information in the image which can irritate the measurement, in other cases small but important differences between various material compounds cannot be detected as images are limited by contrast information and resolution of primary scanning beam. Furthermore, accuracy in secondary electron based metrology is limited by charging. To gather the exact required information for certain material compound as needed, a technique, known from material analytic SEM´s has been introduced for inline CDSEM analysis and process control: Low Loss Back Scattered Electron Imaging (LL-BSE). The key at LL-BSE imaging is the collection of only the back scattered electrons (BSE) from outermost specimen surface which undergo the least amount possible of energy loss in the process of image generation following impact of the material by a primary beam. In LL-BSE very good and measurable material distinction and sensitivity, even for very low density material compounds can be achieved. This paper presents new methods for faster process development cycle, at reduced cost, based on LL-BSE mass data mining instead of sending wafers for destructive material analysis.

Solving next generation (1x node) metrology challenges using advanced CDSEM capabilities: tilt, high energy and backscatter imaging

Traditional metrology solutions are facing a range of challenges at the 1X node such as three dimensional (3D) measurement capabilities, shrinking overlay and critical dimension (CD) error budgets driven by multi-patterning and via in trench CD measurements. Hybrid metrology offers promising new capabilities to address some of these challenges but it will take some time before fully realized. This paper explores new capabilities currently offered on the in-line Critical Dimension Scanning Electron Microscope (CD-SEM) to address these challenges and enable the CD-SEM to move beyond measuring bottom CD using top down imaging. Device performance is strongly correlated with Fin geometry causing an urgent need for 3D measurements. New beam tilting capabilities enhance the ability to make 3D measurements in the front-end-of-line (FEOL) of the metal gate FinFET process in manufacturing. We explore these new capabilities for measuring Fin height and build upon the work communicated last year at SPIE1. Furthermore, we extend the application of the tilt beam to the back-end-of-line (BEOL) trench depth measurement and demonstrate its capability in production targeting replacement of the existing Atomic Force Microscope (AFM) measurements by including the height measurement in the existing CDSEM recipe to reduce fab cycle time. In the BEOL, another increasingly challenging measurement for the traditional CD-SEM is the bottom CD of the self-aligned via (SAV) in a trench first via last (TFVL) process. Due to the extremely high aspect ratio of the structure secondary electron (SE) collection from the via bottom is significantly reduced requiring the use of backscatter electrons (BSE) to increase the relevant image quality. Even with this solution, the resulting images are difficult to measure with advanced technology nodes. We explore new methods to increase measurement robustness and combine this with novel segmentation-based measurement algorithm generated specifically for BSE images. The results will be contrasted with data from previously used methods to quantify the improvement. We also compare the results to electrical test data to evaluate and quantify the measurement performance improvements. Lastly, according to International Technology Roadmap for Semiconductors (ITRS) from 2013, the overlay 3 sigma requirement will be 3.3 nm in 2015 and 2.9 nm in 2016. Advanced lithography requires overlay measurement in die on features resembling the device geometry. However, current optical overlay measurement is performed in the scribe line on large targets due to optical diffraction limit. In some cases, this limits the usefulness of the measurement since it does not represent the true behavior of the device. We explore using high voltage imaging to help address this urgent need. Novel CD-SEM based overlay targets that optimize the restrictions of process geometry and SEM technique were designed and spread out across the die. Measurements are done on these new targets both after photolithography and etch. Correlation is drawn between the two measurements. These results will also be compared to conventional optical overlay measurement approaches and we will discuss the possibility of using this capability in high volume manufacturing.

Addressing FinFET metrology challenges in 1× node using tilt-beam critical dimension scanning electron microscope

Abstract. At 1× node, a three-dimensional (3-D) FinFET process raises a number of new metrology challenges for process control, including gate height and fin height. At present, there is a metrology gap in inline in-die measurement of these parameters. To fill this metrology gap, in-column beam tilt has been implemented on Applied Materials V4i+ critical dimension scanning electron microscope for height measurement. Low-tilt (5 deg) and high-tilt (14 deg) beam angles have been calibrated to obtain the height and the sidewall angle information. Evaluation of its feasibility and production worthiness is done with applications in both gate height and fin height measurements. Transmission electron microscope correlation with an R2 equal to 0.89 and a precision of 0.81 nm have been achieved on various in-die features in a gate height application. The initial fin height measurement shows less accuracy (R2 being 0.77) and precision (1.49 nm) due to greater challenges brought by the fin profile, yet it is promising for the first attempt. Sensitivity to design of experiment offset die-to-die and in-die variations is demonstrated in both gate height and fin height. The process defect is successfully captured with inline gate height measurement. This is the first successful demonstration of inline in-die gate height measurement for a 14-nm FinFET process control.

Metrology challenges for advanced lithography techniques

Traditionally CD SEM has been positioned as a local critical dimension measurement and analysis technique. Emerging lithography techniques introduce new challenges for CD SEM such as overlay error measurements. For the sub 45 nm technology nodes, several new lithography approaches are developed that rely on multiple lithography and deposition and etch process steps. Seamless integration of these lithography and deposition and etch process steps requires specific CD and/or overlay metrology capability for optimal CD and overlay registration performance. Areas of development are focused on CD measurement algorithms and correlation after resist develop and subsequent etch steps. These new lithography processes require unprecedented accuracy and overlay resolution. Fundamental and application specific metrology challenges and solutions will be highlighted. In addition, this paper will report on unique overlay target design in combination with innovative CD SEM measurement techniques to meet those challenges.

Characterizing and understanding stray tilt: the next major contributor to CD-SEM tool matching

Measurement using electron beam tilt has recently been highlighted as holding the promise of future sidewall angle and thickness determinations in the CD SEM in a manufacturing environment. But even before robust tilted beam measurements can be made, a thorough understanding of stray tilt, its characterization and control, is needed to provide the foundation for tilt calibrations and measurements. Stray tilt is the amount of unintended angular deviation of the electron beam from the normal to the specimens (wafer) surface. Stray tilt is common to all SEMs used in manufacturing due to the following contributors: mechanical tolerances, acting both within the SEM column and between the SEM column and the chamber and the sample holder; and also residual and parasitic magnetic and electrostatic fields - these fields are generated both within and outside of the SEM integrated stand-alone unit. Past characterization attempts addressed this issue through an asymmetry specification. Recent data has suggested that stray tilt errors can have significant negative effects on todays critical dimension measurements, especially on a fleet of CD SEM tools with different amounts of stray tilt. This paper explores the measurement, monitoring and minimizing of stray tilt and the consequences on tool matching.

Buckling characterization of gate all around silicon nanowires

Imaging of suspended silicon nanonwires (SiNW) by SEM reveals that some of the SiNW are buckled. Buckling can impact device performance and it is therefore important to characterize this phenomenon. Measuring the buckling of suspended silicon nanowires (SiNW) poses significant challenges: (1) Small dimensions - SiNW are made with diameters ranging from about 3 to 10 nm and the buckling is of a similar scale. (2) Accurate height measurements – buckling is a three dimensional phenomena. To meet these challenges a new height map reconstruction technique was introduced, using the CDSEM side detectors signal. Measuring pixel by pixel position in X, Y and Z (height) dimensions, we can obtain the buckling vector gradient along the wire in three dimensions. In this paper we present: (1) A description of the height map reconstruction technique used. (2) Three dimensional characterization of SiNW: (a) SiNW buckling measurements (b) Characterization of buckling as a function of the SiNW length and width.

CDSEM focus/dose monitor for product applications

Advanced 193 nm lithographic processes will require defocus control for product wafers in order to meet CD and profile requirements in the future. Dose control is already required. The interaction of product wafer materials with lithography requires additional controls beyond tool monitoring. While scatterometry has demonstrated excellent ability to extract effective defocus and dose information from monitor wafers, the addition of product film stacks introduces several issues for this technique. The additional complexity of model generation and the sensitivity to under-layer thickness and optical property variation are among these. A CDSEM technique for lithography focus monitoring overcomes these issues provided it has sufficient precision and relative accuracy. In this paper, we report on comparative studies of two CDSEM techniques. One technique uses angled e-beam to better view the sidewall for edge width measurement. The angle of the beam from normal incidence is considerably larger than previously explored thereby enabling sensitive measurements on shallower structures. The other technique introduces new target designs particularly suited to CDSEM measurement that have enhanced sensitivity to focus and dose. Implementation of these techniques requires expanded sampling during the course of a single measurement in order to suppress roughness. The small target size of these structures enables applications with targets in product kerf and embedded within the circuit. In summary, these methods enable the measurement of dose and focus variations on product wafers.