Ramanathan Sethuraman

C-HEAP: A Heterogeneous Multi-Processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems

The key issue in the design of Systems-on-a-Chip (SoC) is to trade-off efficiency against flexibility, and time to market versus cost. Current deep submicron processing technologiesenable integration of multiple software programmable processors (e.g., CPUs,DSPs) and dedicated hardware components into a single cost-efficient IC. Ourtop-down design methodology with various abstraction levels helps designingthese ICs in a reasonable amount of time. This methodology starts with a high-levelexecutable specification, and converges towards a silicon implementation.A major task in the design process is to ensure that all components (hardwareand software) communicate with each other correctly. In this article, we tacklethis problem in the context of the signal processing domain in two ways: wepropose a modular, flexible, and scalable heterogeneous multi-processor architecturetemplate based on distributed shared memory, and we present an efficient andtransparent protocol for communication and (re)configuration. The protocolimplementations have been incorporated in libraries, which allows quick traversalof the various abstraction levels, so enabling incremental design. The designdecisions to be taken at each abstraction level are evaluated by means of(co-)simulation. Prototyping is used too, to verify the systems functionalcorrectness. The effectiveness of our approach is illustrated by a designcase of a multi-standard video and image codec.

Application specific instruction-set processor template for motion estimation in video applications

The gap between application specific integrated circuits (ASICs) and general-purpose programmable processors in terms of performance, power, cost and flexibility is well known. Application specific instruction-set processors (ASIPs) bridge this gap. In this work, we demonstrate the key benefits of ASIPs for several video applications. One of the most compute- and memory-intensive functions in video processing is motion estimation (ME). The focus of this work is on the design of a ME template, which is useful for several video applications like video encoding, obstacle detection, picturerate up-conversion, 2-D-to-3-D video conversion, etc. An instruction-set suitable for performing a variety of ME functions is developed. The ASIP is based on a very long instruction word (VLIW) processor template and meets low-power and low-cost requirements still providing the flexibility needed for the application domain. The ME ASIP design consumes 27 mW and takes an area of 1.1 mm/sup 2/ in 0.13 /spl mu/m technology performing picturerate up-conversion, for standard definition (CCIR601) resolution at 50 frames per second.

A low-cost implementation of super-resolution based on a video encoder

This paper presents an approach to improve the quality of digital images over the sensor resolution using superresolution techniques. In order to obtain a feasible low cost implementation, the resources have been restricted to those that can be found in a generic video encoder, i.e.: the motion estimator, the motion compensator, image loop memory, etc. The super-resolution system has been implemented over a codesign platform developed by the Philips Research Laboratories in Eindhoven, while performing minimal changes on the overall hardware architecture. Nevertheless, this methodology can easily be extended to any generic video encoder architecture. The results show important improvements in the image quality, assuming that sufficient sample data is available. Based on these results, some generalizations can be made about the impact of the sampling process on the quality of the super-resolution image.

A technique for reducing complexity of recursive motion estimation algorithms

The recursive search motion estimation algorithm offers smooth and accurate motion vector fields. Computationally, the most expensive part of the motion estimator is the evaluation of the various motion vector candidates. Evaluation is performed by comparing blocks in two consecutive frames indicated by motion vector candidates. The paper addresses the issue of reducing the already extremely low number of motion vector evaluations. We apply preprocessing techniques to reduce the number of motion vector candidates from 7 to 5, i.e. 30%, without sacrificing quality. We exemplify the above findings through experimental results obtained using the 3D recursive search motion estimation algorithm. The required preprocessing overhead is negligible.

An Efficient Picture-Rate Up-Converter

The importance of low-power design is not just critical to portable devices but also to line powered equipment like TV products. Power dissipation strongly influences the price of the chip, since the packaging and cooling costs increase dramatically with increasing power dissipation. In this work, we analyze and optimize algorithm and architecture of a picture rate up-conversion module. We perform algorithm/architecture co-design in which we meet high quality specification while keeping the power dissipation low. In the algorithm front, we focus on the motion estimation which is computationally the most intensive part of the picture-rate up-conversion application. We analyze the following parameters of the motion estimation algorithm: The number of motion estimation iterations per input image pair and the image scanning order of individual iterations. Further, we apply novel pre-processing technique to address the issue of reducing the already extremely low number of motion vector candidate evaluations. However, optimal selection of motion vector candidates is a necessity to achieve high picture quality. In the architectural front, to cope with the large memory bandwidth requirements of the application, we use multi-level caching to exploit locality of reference. Further, we apply data compression to the image data stored in memory, to reduce the memory capacity and bandwidth requirements. Both the above techniques significantly reduce the overall power dissipation.

Low-cost and real-time super-resolution over a video encoder IP

This paper addresses a low-cost and real-time solution for the implementation of super-resolution (SR) algorithms over SOC (System-On-Chip) platforms in order to achieve high-quality image improvements. Low-cost constraints are accomplished in the sense that SR is performed without developing a specific hardware, but re-using a video encoder IP block. This encoder can be used either in compression mode or in SR mode. This video encoder together with the new SR features constitutes an IP block inside Philips Research, upon which several SOC platforms are being developed. Furthermore, this work can be easily adapted to other video encoder platforms.

Low-cost super-resolution algorithms implementation over a HW/SW video compression platform

Two approaches are presented in this paper to improve the quality of digital images over the sensor resolution using super-resolution techniques: iterative super-resolution (ISR) and noniterative super-resolution (NISR) algorithms. The results show important improvements in the image quality, assuming that sufficient sample data and a reasonable amount of aliasing are available at the input images. These super-resolution algorithms have been implemented over a codesign video compression platform developed by Philips Research, performing minimal changes on the overall hardware architecture. In this way, a novel and feasible low-cost implementation has been obtained by using the resources encountered in a generic hybrid video encoder. Although a specific video codec platform has been used, the methodology presented in this paper is easily extendable to any other video encoder architectures. Finally a comparison in terms of memory, computational load, and image quality for both algorithms, as well as some general statements about the final impact of the sampling process on the quality of the super-resolved (SR) image, are also presented.

A low-cost and low-power multi-standard video encoder

Video encoders are an important IP block in mobile multimedia systems. In this paper, we describe a low-cost low-power multi-standard (MPEG4, JPEG, and H.263) video/image encoder. The low-cost and low-power aspects are achieved by the right choice of algorithms and architectures. In the algorithm front, an embedded compression technique for reducing the size of loop memory has enabled a single-chip low-cost realization of the encoder. Further, the hardware components that accelerate the kernels of encoding are implemented as application specific instruction-set processors (ASIPs) thereby providing flexibility to address multi-standard encoding. The power and area estimates for the encoder for QCIF@15fps in 0.18 /spl mu/m CMOS technology are 30 mW and 20 mm/sup 2/ respectively including the loop memory.

A cost-effective implementation of object-based motion estimation

Emerging applications in the mobile and automotive industries can benefit from a solution which can segment an image into objects. Although originally not developed for these applications, object-based motion estimation (OME) is an algorithm which provides such a segmentation. We map this algorithm on an application specific instruction processor (ASIP) based on a very long instruction word (VLIW) template. An analysis of the computational requirements is made, using video format conversion as an application, since emerging applications are not available yet. We also propose a multi-level caching architecture to keep bandwidth and power requirements low and discuss algorithmic changes to OME, which are necessary for OME to be mapped on an ASIP VLIW. A quality comparison of the resulting vector fields is made as well.

Mapping of real-time and low-cost super-resolution algorithms onto a hybrid video encoder

This paper focuses on the mapping of low-cost and real-time super-resolution (SR) algorithms onto SOC (System-On-Chip) platforms in order to achieve high-quality image improvements. Low-cost constraints are accomplished by avoiding the need for specific SR hardware, by re-using a video encoder architecture. Only small modifications are needed for: the motion estimator, the motion compensator, image loop memory, etc. This encoder can be used either in compression mode or in SR mode. This video encoder together with the new SR features constitutes an IP block inside Philips Research, upon which several SOC platforms are being developed. Although this SR algorithm has been implemented on an encoder architecture developed by Philips Research it can be easily mapped upon other hybrid video encoder platforms. The results show important improvements in the image quality. Based on these results, some generalizations can be made about the impact of the sampling process on the quality of the super-resolution image.