Carlos Antonio Alba Pinto

Heterogeneous multiprocessor for high definition video

This work presents the heterogeneous multiprocessor capable of processing HDTV material (1920*1080i at 60 Hz) in the domain of motion estimation based TV applications. In particular, it is targeted to the state-of-the-art format conversion and scan-rate conversion functions like de-interlacing and picture-rate up-conversion. The heterogeneous multiprocessor consists of five processors communicating through fifos and shared memories. The highest picture quality level that meets the HDTV real-time performance was enabled by: judicious choice of application task partitioning; right choice of instruction set architecture for the VLIW-based multiprocessor; exploitation of the customized two level memory hierarchy (the search area scratchpad and the region scratchpad). Furthermore, the heterogeneous multiprocessor offers high degree of flexibility: size and aspect ratio of the region and the search area scratchpads; algorithm for selection of the motion vector candidates; algorithm for post-processing of the motion vector field; plethora of interpolation schemes used in motion estimation and compensation offering trade-off between interpolation complexity and number of interpolated pixels in parallel.

HiveFlex-Video VSP1: Video Signal Processing Architecture for Video Coding and Post-Processing

As mobile displays proliferate across the world, and fixed video displays expand in size, consumers demand enhanced visual experiences while watching such displays. Competitive low-end to high-end markets are migrating to high-definition (HD) output displays driven by consumer demand. In order to generate high quality visual experiences on HD displays, video processing algorithms are becoming increasingly complex. Such complex HD algorithms require up to tera-operations per second to generate acceptable HD video output. Silicon Hives HiveFlex Video VSP1 processor services the needs all low to high end video displays by using a unique scaleable tiled architecture. The architecture of each tile is flexible, low-cost and low-power, resulting in an attractive IP solution targeting consumer video signal processing (VSP) systems on chips (SoCs). The Video VSPI tile presented here performs a variety of video coding algorithms commonly used in post processing of HDTV signals such as H.264 decoding, de-interlacing, picture-rate up-conversion and others. H.264 or MPEG4-AVC is an advanced video coding standard targeting multiple markets such as broadcast and hand-held entertainment. In partnership with Silicon Hive, AllGo Embedded Systems has developed an H.264 decoder that is optimized for the HiveFlex VSP architecture. Multiple VSP tiles with configurable number of issue slots and SIMD architecture are used efficiently to implement H.264 video decoding at HD resolution

HiveFlex Video VSP1 Demonstration

This work presents a real-time demonstrator system for the VSP1 Tile. The complete 8-way SIMD VSP1 Tile is implemented on the demonstration platform based on the Xilinx Virtex2 XC2V8000 FPGA chip. The application running on a VSP1 Tile is spatial up-scaling. This is a challenging application since it is based on a pixel-based algorithm using content adaptive filtering. The FPGA running on 25 MHz is capable of achieving 17.3 fps for input sequence (320*192) producing four times bigger output sequence (640*384)