Rami Fathy

Feedback flow to improve model-based OPC calibration test patterns

Process models are responsible for the prediction of the latent image in the resist in a lithographic process. In order for the process model to calculate the latent image, information about the aerial image at each layout fragment is evaluated first and then some aerial image characteristics are extracted. These parameters are passed to the process models to calculate wafer latent image. The process model will return a threshold value that indicates the position of the latent image inside the resist, the accuracy of this value will depend on the calibration data that were used to build the process model in the first place. The calibration structures used in building the models are usually gathered in a single layout file called the test pattern. Real raw data from the lithographic process are measured and attached to its corresponding structure in the test pattern, this data is then applied to the calibration flow of the models. In this paper we present an approach to automatically detect patterns that are found in real designs and have considerable aerial image parameters differences with the nearest test pattern structure, and repair the test patterns to include these structures. This detect-and-repair approach will guarantee accurate prediction of different layout fragments and therefore correct OPC behavior.

Through-process modeling in a DfM environment

In recent years, design for manufacturability (DfM) has become an important focus item of the semiconductor industry and many new DfM applications have arisen. Most of these applications rely heavily on the ability to model process sensitivity and here we explore the role of through-process modeling on DfM applications. Several different DfM applications are examined and their lithography model requirements analyzed. The complexities of creating through-process models are then explored and methods to ensure their accuracy presented.

Litho aware method for circuit timing/power analysis through process

Device extraction and the quality of device extraction is becoming of increasing concern for integrated circuit design flow. As circuits become more complicated with concomitant reductions in geometry, the design engineer faces the ever burgeoning demand of accurate device extraction. For technology nodes of 65nm and below approximation of extracting the device geometry drawn in the design layout polygons might not be sufficient to describe the actual electrical behavior for these devices, therefore contours from lithographic simulations need to be considered for more accurate results. Process window variations have a considerable effect on the shape of the device wafer contour, having an accurate method to extract device parameters from wafer contours would still need to know which lithographic condition to simulate. Many questions can be raised here like: Are contours that represent the best lithography conditions just enough? Is there a need to consider also process variations? How do we include them in the extraction algorithm? In this paper we first present the method of extracting the devices from layout coupled with lithographic simulations. Afterwards a complete flow for circuit time/power analysis using lithographic contours is described. Comparisons between timing results from the conventional LVS method and Litho aware method are done to show the importance of litho contours considerations.

Optimization of process window simulations for litho-friendly design framework

Cutting edge technology node manufacturers are always researching how to increase yield while still optimally using silicon wafer area, this way these technologies will appeal more to designers. Many problems arise with such requirements, most important is the failure of plain layout geometric checks to capture yield limiting features in designs, if these features are recognized at an early stage of design, it can save a lot of efforts at the fabrication end. A new trend of verification is to couple geometric checks with lithography simulations at the designer space. A lithography process has critical parameters that control the quality of its resulting output. Unfortunately some of these parameters can not be kept constant during the exposure process, and the variability of these parameters should be taken into consideration during the lithography simulations, and the lithography simulations are performed multiple times with these variables set at the different values they can have during the actual process. This significantly affects the runtime for verification. In this paper the authors are presenting a methodology to carefully select only needed values for varying lithography parameters; that would capture the process variations and improve runtime due to reduced simulations. The selected values depend on the desired variation for each parameter considered in the simulations. The method is implemented as a tool for qualification of different design techniques.

The effect of calibration feature weighting on OPC optical and resist models : investigating the influence on model coefficients and on the overall model fitting

Performing model based optical proximity correction (MB-OPC) is an essential step in the production of advanced integrated circuits that are manufactured with optical lithography technology. The accuracy of these models depends highly on the experimental data used in the model development (model calibration) process. The calibration features are weighted relative to each other depending on many aspects, this weighting plays an important role in the accuracy of the developed models. In this paper, the effect of the feature weighting on OPC models is studied. Different weighting schemes are introduced and the effect on both the optical and resist models (specifically the resist model coefficients) is presented and compared. The effect of the weighting on the overall model fitting was also investigated.

Yield enhancement flow for analog and full custom designs reliability-rules automatic application

As the variations of shrunk processes increase at rapid rate, the performance of fabricated analog and full custom chips remarkably fluctuate. This paper describes an effective automatic flow for reliability rules automatic application onto analog and full-custom ASIC designs, without introducing any new design rules check (DRC) violations in input design. This Yield enhancement flow has shown good improvements on used test designs, and ran in reasonable time. Based on the standardization methodology used, additional foundry Yield-enhancement-related recommendations can be also developed as extension to this flow seamlessly providing easy and quick new technology adoption and short Turnaround Time (TAT).

Schematic-driven physical verification: Fully automated solution for analog IC design

Designing ICs (integrated circuits) is inherently a complex task involving human expertise as well as aids intended to accelerate the process. A fundamental requirement for design success is a clear strategy that coordinates the entire design flow from specifications to a marketable product. Modem VLSI (very large scale integration) IC designs, especially analog/mixed signal LSIs, must meet various design and electrical constraints such as IR-drop, cross-talk, low power and low voltage design. This complexity poses several physical design challenges for specific analog structures such as device symmetry, net matching and more. Therefore it is essential to have some form of communication between the front-end designers (schematic and transistor level) and the physical layout engineers. The current process involves the front-end designer placing the design constraints in the form of annotations on the schematic netlist. These annotations are then passed to the layout team for manual implementation followed by visual verification only. This paper explores a new methodology providing a fully automated CAD flow that captures the designers intent from the schematic netlist, links these annotations to the proper devices or nets on the physical layout level, then runs verification checks using the Calibre R tool suite. Several applications can be used with the proposed flow, in this work we will present an application specifically for capturing design constraints related to physical layout recommendations, tested on Opamp circuit.

Smart double-cut via insertion flow with dynamic design-rules compliance for fast new technology adoption

As IC technologies shrink and via defects remain the same size, the probability of via defects increases. Redundant via insertion is an effective method to reduce yield loss related to via failures, but a large number of extremely complex design rules make efficient automatic via insertion difficult. This paper introduces an automatic redundant via insertion flow which is capable of adopting new technologies and complex design rules extremely quickly. Runtime and efficiency are optimized through a smart insertion scheduling technique. Our experiments show that it efficiently improves redundant via percentage, making designs more robust against via defects.

An electrical-aware parametric DFM solution for analog circuits

Today, many of the approaches that are commonly referred to as physical DFM techniques only address catastrophic defects and systematic process variations. These techniques include spreading wires, doubling vias, identification of critical areas in the circuit that are especially susceptible to defects, and identification of proximity effects caused by the lithography process. However, physical DFM tools are purely “geometric”, in that they work to preserve shape fidelity without any knowledge of the impact on the electrical characteristics of the shapes that are manufactured in silicon. While these techniques have proven useful in reducing functional failures and increasing overall yield by a few percentage points, they completely ignore the more important category of parametric failures. The proposed solution presented in this chapter specifically helps to address the parametric performance modeling problems encountered at smaller geometries. As this solution drives design requirements into physical layout design and moves layout awareness upstream into design, useful information about the design (on the physical and electrical level) is captured, analyzed, and simulated. Deviations in the electrical characteristics due to physical layout and process variations, are identified and highlighted on the design. These deviations are referred as electrical hotspots (e-hotspots). To validate this work, The proposed e-hotspot detection engine is verified against silicon wafer data for a level shifter circuit designed at 130nm. The e-hotspot devices with high variation in DC current and causing parametric failure, are identified.

Pre-OPC layout decomposition for improved image fidelity

In microelectronics manufacturing, photolithography is the art of transferring pattern shapes printed on a mask to silicon wafers by the use of special imaging systems. These imaging systems stopped reducing exposure wavelength at 193nm. However, the industry demand for tighter design shapes and smaller structures on wafer has not stopped. To overcome some of the restrictions associated with the photographic process, new methods for Resolution Enhancement Techniques (RET) are being constantly explored and applied. An essential step in any RET method is Optical Proximity Correction (OPC). In this process the edges of the target desired shapes are manipulated to compensate for light diffraction effects and result in shapes on wafer as close as possible to the desired shapes. Manipulation of the shapes is always restricted by Mask Rules Checks (MRCs). The MRCs are the rules that assure that the pattern coming out of OPC can be printed on the mask without any catastrophic faults. Essential as they are, MRCs also place constrains on the solutions explored by the OPC algorithms. In this paper, an automated algorithm has been implemented to overcome MRC limitations to RET by decomposing the original layout at the places where regular RET hit the MRC during OPC.This algorithm has been applied to test cases where simulation results showed much better printability than the normal conventional solutions. This solution has also been tested and verified on silicon.