Mohamed Dessouky

Synthesis of CMOS Analog Cells Using AMIGO

In this paper, a simulation-based synthesis tool, AMIGO, for analog cell sizing is presented. AMIGO is based upon genetic optimization techniques adapted to circuit sizing. A framework has been developed using TCL/TK language that allows the designer to set the optimization problem, define complex constraint functions, watch the progress of optimization, and finally view results. To increase design reliability a sizing-rule pre-processor is incorporated in the tool to automatically generate topology related constraints specific to analog building blocks. Different approaches of using circuit optimizers are demonstrated through the synthesis of three different analog cells: a latched-type comparator, a folded cascode opamp and a switched-capacitor integrator. AMIGO showed to be a successful synthesis tool that can be part of a more general synthesis/migration flow.

A fully automated approach for analog circuit reuse

Demonstrated in this paper is a technique for automatic circuit resizing between different technologies. This technology is not based on any optimization techniques, but rather relies on a new algorithm based on knowledge extraction, which makes it a very fast technique. This technique studies the original design and extracts its major features (basic devices & blocks features, device matching, parasitics, and symmetry) and then reproduces a new sized design in the target technology with the same performance as the original design. The migration of a low voltage delta sigma A/D is presented in this paper to validate the migration engine.

Tunable bandpass sigma delta modulators

This paper examines different designs for tunable bandpass sigma delta modulators. Both discrete and continuous time implementations are considered. Comparison between different tuning methods is demonstrated using MATLAB simulations. Results show that discrete time modulators using variable coefficients are best suited for tunability

Switch sizing for very low-voltage switched-capacitor circuits

A simple series switch sizing procedure is presented taking into account very low-voltage switch operation. Under these conditions, the switch conducts not only in the linear region, but also in saturation. The procedure has been implemented in an automatic sizing tool and used to optimize separately switch sizes in a very low-voltage delta-sigma modulator. This has allowed us to minimize clock feedthrough while satisfying all settling requirements.

Architecture of a Fully Digital CDR for Plesiochronous Clocking Systems

This paper describes a design of a fully digital clock and data recovery (CDR) system with plesiochronous clocking. Besides the well known advantages of digital implementations over analog ones in terms of robustness against process and temperature variations, scalability, compactness and low cost, the system also enjoys many features. It can withstand an input data cycle-to-cycle jitter up to ±37.5% UI. Data are obtained through digital correlation with the incoming symbol instead of ordinary sampling at the middle of the eye pattern, which improves BER. Furthermore, it needs only, at worst, three preamble bits to get into lock. It is insensitive to long runs of transition-free data patterns. The extracted data clock is not shifted as long as input data jitter is small (typically less than ±12.5% UI), thus, minimizing jitter in the extracted data clock. Besides, the extracted clock has a 50% duty cycle.

Extended division range 2/3 chain frequency divider with dynamic control word

This paper presents a 4–31 programmable frequency divider with dynamic control word built in 90 nm CMOS. The divider uses a chain of 2/3 dual modulus pre-scalar cells. This paper presents a modification to the conventional 2/3 dual modulus pre-scalar building cell. This modification allows changing the control word dynamically during the operation. The divider consists of a chain of four 2/3 dual modulus cells. The maximum operating frequency is 7.9 GHz consuming 24.5 mA at a low voltage supply of IV.

13-bit 205 MS/s time-interleaved pipelined ADC with digital background calibration

This paper presents a 1.0-V 13-bit 205-MSample/s double-sampled pipelined analog-to-digital converter (ADC) with a 95-dB spurious free dynamic range (SFDR), a 75.5-dB signal-to-noise-plus-distortion ratio (SNDR) over the full Nyquist band and a total power consumption of 71mW. This performance is enabled by digital background calibration of both capacitor mismatch in the multi-bit DAC and finite inter-stage gain errors. M-sequence characteristics was used for the generation of the multiple orthogonal codes needed in the calibration engine. Also, a simple design for the dithered re-quantizer which precedes calibration is adopted. Digital calibration achieves an improvement of better than 23-dB in SFDR and 13-dB in SNDR.

Optimization of the output power of a frequency-up conversion piezoelectric energy harvester

A mechanical stopper-based frequency up-conversion, FUC, piezoelectric energy harvester is designed for low frequency wideband vibrations. The primary low frequency beam is designed to have a resonance frequency as low as 15.6 Hz. Frequency up-conversion is achieved by a harvesting stopper beam which has a higher resonance frequency around 200 Hz. The effect of changing the impact point between the two beams is investigated by FEM simulations for further output power optimization. In case of using PVDF beams, the tip displacement of the stopper beam is increased from 13 μm to 32 μm when the length of the lateral overlap between the two beams is decreased from 50% to 3% of the stopper beam length for an input acceleration of 0.1g. This corresponds to a theoretical output open circuit voltage increase from 0.8V to 1.9V and a corresponding 6 times increase in the output power of the stopper beam. This proves the intuitive relationship between the effective stiffness of the two beams in the coupled vibrations phase and the position of the point of impact along the stopper.

An 8Gbps discrete time linear equalizer in 40nm CMOS technology

This paper introduces a new circuit technique for a discrete-time linear equalizer that can be used with current-integrating decision feedback equalizers. The DTLE samples and amplifies the input data in a clock phase then holds the output data in the other clock phase. The latter is the integrating phase of a current-integrating DFE. The DTLE is designed for a half-rate 8-Gbps serial-link receiver equalizer in 40-nm CMOS technology and draws 190-uW from a 1.1-V supply. The technique uses clocked current sources improving the power consumption.

An 8kb SRAM macro in 65nm for ultra-low voltage applications operating from 1.2V to 0.5V

Low-voltage operation for SRAM memories is attractive because it decreases leakage and active power. Hence, energy constrained applications, where performance requirements are not aggressive benefit significantly from an SRAM that offers read and write functionality at the lowest possible supply voltage. This paper explores the limits of low-voltage operation for traditional SRAM and periphery circuits. Read and Write assist techniques are implemented to reach such a low voltage with a 6T bitcell. A test macro of 8-Kbit is designed in 65nm CMOS technology. Simulations show that the design is capable of working down to 0.5V with a frequency of 380-KHz at the worst process corner.