Ramin Farjadrad

A 0.3-/spl mu/m CMOS 8-Gb/s 4-PAM serial link transceiver

An 8-Gb/s 0.3-/spl mu/m CMOS transceiver uses multilevel signaling (4-PAM) and transmit pre-shaping in combination with receive equalization to reduce ISI due to channel low-pass effects. High on-chip frequencies are avoided by multiplexing and demultiplexing the data directly at the pads. Timing recovery takes advantage of a novel frequency acquisition scheme and a linear PLL with a loop bandwidth >30 MHz, phase margin >48/spl deg/ and capture range of 20 MHz without a frequency acquisition aid. The transmitted 8-Gbps data is successfully detected by the receiver after a 10-m coaxial cable. The 2 mm/spl times/2 mm chip consumes 1.1 W at 8 Gbps with a 3-V supply.

A 0.5-/spl mu/m CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling

A 4-Gbit/s serial link transceiver is fabricated in a MOSIS 0.5-/spl mu/m HPCMOS process. To achieve the high data rate without speed critical logic on chip, the data are multiplexed when transmitted and immediately demultiplexed when received. This parallelism is achieved by using multiple phases tapped from a PLL using the phase spacing to determine the bit time. Using an 8:1 multiplexer yields 4 Gbits/s, with an on-chip VCO running at 500 MHz. The internal logic runs at 250 MHz. For robust data recovery, the input is sampled at 3/spl times/ the bit rate and uses a digital phase-picking logic to recover the data. The digital phase picking can adjust the sample at the clock rate to allow high tracking bandwidth. With a 3.3-V supply, the chip has a measured bit error rate (BER) of <10/sup -14/.

A 0.4-/spl mu/m CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter

A serial link transmitter fabricated in a large-scale integrated 0.4-/spl mu/m CMOS process uses multilevel signaling (4-PBM) and a three-tap pre-emphasis filter to reduce intersymbol interference (ISI) caused by channel low-pass effects. Due to the process-limited on-chip frequency, the transmitter output driver is designed as a 5:1 multiplexer to reduce the required clock frequency to one-fifth the symbol rate, or 1 GHz. At 5 Gsym/s (10 Gbis), a data eye opening with a height >350 mV and a width >100 ps is achieved at the source. After 10 m of a copper coaxial cable (PE142LL), the eye opening is reduced to 200 mV and 90 ps with pre-emphasis, and to zero without filtering, The chip dissipates 1 W with a 3.3-V supply and occupies 1.5/spl times/2.0 mm/sup 2/ of die area.

10G | 5G | 2.5G | 1G | 100M physical layer PHY: HOT CHIPS 2015 conference

This article consists of a collection of slides from the authors conference presentation. The ever growing data requirements in the cloud and mobility are creating a bandwidth constraint in global IT infrastructure. In 2012, Aquantia focused on adding 2.5G/5G speeds on Cat5e/Cat6 Links to address the next generation wireless access bottleneck. Aquantias five speed ICs (single, dual, and quad) are the only commercially available NBASE-T compliant ICs since 2013. Five speed ICs from Aquantia has been shipping in large volumes in all major switch and AP platforms since 2014.

Low-power high-density 10GBASE-T ethernet transceiver

This article consists of a collection of slides from the authors conference presentation on low power high-density, 10GBASE-T Ethernet transceivers. Some of the specific topics discussed include: the historical development of Ethernet; markets for Ethernet technology; processing and communications switching capabilities; 10GBase T technical requirements and processing capabilities; design challenges; LDPC architecture and wire complexity; noise measurement and cancellation techniques; Tx DAC/Hybrid architectures; the deploying of cloud storage; and future areas of technological development.