Chih-Kong Ken Yang

A 0.3-/spl mu/m CMOS 8-Gb/s 4-PAM serial link transceiver

An 8-Gb/s 0.3-/spl mu/m CMOS transceiver uses multilevel signaling (4-PAM) and transmit pre-shaping in combination with receive equalization to reduce ISI due to channel low-pass effects. High on-chip frequencies are avoided by multiplexing and demultiplexing the data directly at the pads. Timing recovery takes advantage of a novel frequency acquisition scheme and a linear PLL with a loop bandwidth >30 MHz, phase margin >48/spl deg/ and capture range of 20 MHz without a frequency acquisition aid. The transmitted 8-Gbps data is successfully detected by the receiver after a 10-m coaxial cable. The 2 mm/spl times/2 mm chip consumes 1.1 W at 8 Gbps with a 3-V supply.

A 0.5-/spl mu/m CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling

A 4-Gbit/s serial link transceiver is fabricated in a MOSIS 0.5-/spl mu/m HPCMOS process. To achieve the high data rate without speed critical logic on chip, the data are multiplexed when transmitted and immediately demultiplexed when received. This parallelism is achieved by using multiple phases tapped from a PLL using the phase spacing to determine the bit time. Using an 8:1 multiplexer yields 4 Gbits/s, with an on-chip VCO running at 500 MHz. The internal logic runs at 250 MHz. For robust data recovery, the input is sampled at 3/spl times/ the bit rate and uses a digital phase-picking logic to recover the data. The digital phase picking can adjust the sample at the clock rate to allow high tracking bandwidth. With a 3.3-V supply, the chip has a measured bit error rate (BER) of <10/sup -14/.

A 0.4-/spl mu/m CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter

A serial link transmitter fabricated in a large-scale integrated 0.4-/spl mu/m CMOS process uses multilevel signaling (4-PBM) and a three-tap pre-emphasis filter to reduce intersymbol interference (ISI) caused by channel low-pass effects. Due to the process-limited on-chip frequency, the transmitter output driver is designed as a 5:1 multiplexer to reduce the required clock frequency to one-fifth the symbol rate, or 1 GHz. At 5 Gsym/s (10 Gbis), a data eye opening with a height >350 mV and a width >100 ps is achieved at the source. After 10 m of a copper coaxial cable (PE142LL), the eye opening is reduced to 200 mV and 90 ps with pre-emphasis, and to zero without filtering, The chip dissipates 1 W with a 3.3-V supply and occupies 1.5/spl times/2.0 mm/sup 2/ of die area.

Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops

This paper describes two techniques for designing phase-frequency detectors (PFDs) with higher operating frequencies (periods of less than 8x the delay of a fan-out-4 inverter (FO-4)) and faster frequency acquisition. Prototypes designed in 0.25-µm CMOS process exhibit operating frequencies of 1.25 GHz ( = 1/(8 ċ FO-4) ) and 1.5 GHz ( = 1/(6.7 ċ FO-4) ) for two techniques respectively whereas a conventional PFD operates < 1 GHz ( = 1/(10 ċ FO-4) ). The two proposed PFDs achieve a capture range of 1.7x and 1.2x the conventional design.

Jitter optimization based on phase-locked loop design parameters

A tunable PLL allows independent optimization of loop parameters. The effects of varying PLL parameters (damping factor and bandwidth) on timing jitter is derived analytically and verified experimentally.

A 0.8-/spl mu/m CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links

A receiver targeting OC-48 (2.488 Gb/s) serial data link has been designed and integrated in a 0.8-/spl mu/m CMOS process. An experimental receiving front-end circuit demonstrates the viability of using multiple phased clocks to overcome the intrinsic gate-speed limitations in the demultiplexing (receiving) and multiplexing (transmitting) of serial data. To perform clock recovery, data is 3/spl times/ oversampled so that transitions can be detected to determine bit boundaries. The design of a transmitter for the high-speed serial data is also described. The complete transceiver occupies a die area of /spl sim/3/spl times/3 mm/sup 2/.

A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation

This paper describes a fully integrated low-jitter CMOS phase-locked loop and clock buffer for low-power digital systems with a wide range of operating frequencies. The design uses static CMOS inverters as a building block of the voltage-controlled oscillator and clock buffering. To reduce supply-induced jitter, programmable circuits with opposite sensitivity compensate for the delay variations. Both elements have supply-induced delay sensitivity of /spl les/0.1%-delay/1%-V/sub DD/. The design is fabricated in 0.25-/spl mu/m CMOS technology and consumes 10mW from a 2.5-V supply. The experimental results verify that the proposed methods significantly improve the jitter.

Offset compensation in comparators with minimum input-referred supply noise

The resolution of a comparator is determined by the dc input offset and the ac noise. For mixed-mode applications with significant digital switching, input-referred supply noise can be a significant source of error. This paper proposes an offset compensation technique that can simultaneously minimize input-referred supply noise. Demonstrated with digital offset compensation, this scheme reduces input-referred supply noise to a small fraction (13%) of one least significant bit (LSB) digital offset. In addition, the same analysis can be applied to analog offset compensation.

A serial-link transceiver based on 8 GSample/s A/D and D/A converters in 0.25 /spl mu/m CMOS

On-chip VCOs generate 16 clock phases that drive an 8-way interleaved 4b A/D input receiver and an 8-way interleaved 8b D/A transmitter. 4 GHz bandwidth is achieved by inductors that distribute the I/O capacitance and a transmit equalizer. Digital calibration adjusts the sample timing to 10 ps, the input and output accuracy to <1 LSB and 3 LSBs, respectively.

GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link

A 4-bit 12-GSample/sec A/D converter (GAD) has been fabricated in a 0.25-/spl mu/m CMOS process to investigate the design of an equalized multi-level link. Clocked differential amplifiers were used to sample the input, followed by high-speed comparators with current-summed offset cancellation. Input bandwidth was measured at 2.5 GHz. Eight 1.5-GSample/sec flash A/D converters were interleaved to achieve the aggregate sample rate.