Ramona Ecke

Copper Oxide Films Grown by Atomic Layer Deposition from Bis(tri-n-butylphosphane)copper(I)acetylacetonate on Ta, TaN, Ru, and SiO2

The thermal atomic layer deposition (ALD) of copper oxide films from the nonfluorinated yet liquid precursor bis(tri-n-butylphosphane)copper(I)acetylacetonate, [( n Bu 3 P) 2 Cu(acac)], and wet O 2 on Ta, TaN, Ru, and SiO 2 substrates at temperatures of < 160°C is reported. Typical temperature-independent growth was observed at least up to 125°C with a growth-per-cycle of ∼0. A for the metallic substrates and an ALD window extending down to 100°C for Ru. On SiO 2 and TaN, the ALD window was observed between 110 and 125°C, with saturated growth shown on TaN still at 135°C. Precursor self-decomposition in a chemical vapor deposition mode led to bimodal growth on Ta, resulting in the parallel formation of continuous films and isolated clusters. This effect was not observed on TaN up to ∼130°C and neither on Ru or SiO 2 for any processing temperature. The degree of nitridation of the tantalum nitride underlayers considerably influenced the film growth. With excellent adhesion of the ALD films on all substrates studied, the results are a promising basis for Cu seed layer ALD applicable to electrochemical Cu metallization in interconnects of ultralarge-scale integrated circuits.

Development of PECVD WN x ultrathin film as barrier layer for copper metallization

A PECVD process for WNx deposition was developed to deposit ultrathin films of 10-nm thickness using a WF6-N2-H2 gas mixture. This paper deals with the influence of several process parameters such as temperature, RF power and gas flows on the deposition rate. For a stable deposition process of ultrathin films, a low deposition rate with controllable parameters is required. All deposited WNx films have a X-ray amorphous microstructure and the fluorine content in the film is very low. Their electrical resistivity is around 200 µΩ cm and almost independent of the film composition and the film thickness. This is why it is a promising diffusion barrier.

High-performance giant magnetoresistive sensorics on flexible Si membranes

We fabricate high-performance giant magnetoresistive (GMR) sensorics on Si wafers, which are subsequently thinned down to 100 μm or 50 μm to realize mechanically flexible sensing elements. The performance of the GMR sensors upon bending is determined by the thickness of the Si membrane. Thus, bending radii down to 15.5 mm and 6.8 mm are achieved for the devices on 100 μm and 50 μm Si supports, respectively. The GMR magnitude remains unchanged at the level of (15.3 ± 0.4)% independent of the support thickness and bending radius. However, a progressive broadening of the GMR curve is observed associated with the magnetostriction of the containing Ni81Fe19 alloy, which is induced by the tensile bending strain generated on the surface of the Si membrane. An effective magnetostriction value of λs = 1.7 × 10−6 is estimated for the GMR stack. Cyclic bending experiments showed excellent reproducibility of the GMR curves during 100 bending cycles.

Effect of annealing on the microstructure of ultrathin tungsten nitride diffusion barriers for copper metallization

Microstructure, phase composition and interface properties of 10- and 50-mm thick CVD-deposited W-N layers covered with Cu were investigated. Phase formation and structural changes of the layer stacks occurring at elevated temperatures (450-600 °C) were correlated. The initially amorphous barriers undergo an abrupt crystallization between 550 °C/1 h and 600 °C/1 h anneals in vacuum. Further annealing at 600 °C up to 16 h leads to changes in the layer configuration such as N redistribution and Cu agglomeration. No signs of significant Cu diffusion through the barriers were observed for the performed anneals up to 600 °C/16 h.

3D integration approaches for MEMS and CMOS sensors based on a Cu through-silicon-via technology and wafer level bonding

Technologies for the 3D integration are described within this paper with respect to devices that have to retain a specific minimum wafer thickness for handling purposes (CMOS) and integrity of mechanical elements (MEMS). This implies Through-Silicon Vias (TSVs) with large dimensions and high aspect ratios (HAR). Moreover, as a main objective, the aspired TSV technology had to be universal and scalable with the designated utilization in a MEMS/CMOS foundry. Two TSV approaches are investigated and discussed, in which the TSVs were fabricated either before or after wafer thinning. One distinctive feature is an incomplete TSV Cu-filling, which avoids long processing and complex process control, while minimizing the thermomechanical stress between Cu and Si and related adverse effects in the device. However, the incomplete filling also includes various challenges regarding process integration. A method based on pattern plating is described, in which TSVs are metalized at the same time as the redistribution layer and which eliminates the need for additional planarization and patterning steps. For MEMS, the realization of a protective hermetically sealed capping is crucial, which is addressed in this paper by glass frit wafer level bonding and is discussed for hermetic sealing of MEMS inertial sensors. The TSV based 3D integration technologies are demonstrated on CMOS like test vehicle and on a MEMS device fabricated in Air Gap Insulated Microstructure (AIM) technology.

Investigation of barrier formation and stability of self-forming barriers with CuMn, CuTi and CuZr alloys

In this work, we present the recent work on self-forming barriers. Focus on investigation laid on the barrier formation and its stability against copper diffusion. The investigated alloys were Cu(Mn), Cu(Ti) and Cu(Zr) respectively. It can be shown that these alloys are capable to form an enrichment layer on the SiO2 interface. Here the substrate influences mainly the thickness of the generated barrier. Electrical measurements show the barrier stability against copper diffusion. Mn and Ti are promising elements as barrier materials.

Influence of SiH 2 on the WN x -PECVD process

Silane was added to an existing WNx PECVD process in different flow ratios to the WF6, to obtain higher thermal stability of the barrier in comparison to the WNx. The deposition rate rises drastically with increased SiH4/WF6 ratios. The ternary compositions were investigated with regard to the sheet resistance and thickness. The X-ray diffraction (XRD) measurements of selected layers with low electrical resistivities in the as-deposited state show a broad amorphous peak like the WNx barrier, indicating an amorphous structure. After characterising the as-deposited state of these samples, thermal treatments of the layers were performed at temperature of 600 °C for 1 h in vacuum.

Atomic layer deposition of ultrathin Cu2O and subsequent reduction to Cu studied by in situ x-ray photoelectron spectroscopy

The growth of ultrathin (<5 nm) Ru-doped Cu2O films deposited on SiO2 by atomic layer deposition (ALD) and Cu films by subsequent reduction of the Cu2O using HCO2H or CO is reported. Ru-doped Cu2O has been deposited by a mixture of 16: 99 mol. % of [(nBu3P)2Cu(acac)] as Cu precursor and 17: 1 mol. % of [Ru(η5-C7H11)(η5-C5H4SiMe3)] as Ru precursor. The catalytic amount of Ru precursor was to support low temperature reduction of Cu2O to metallic Cu by formic acid (HCO2H) on arbitrary substrate. In situ x-ray photoelectron spectroscopy investigations of the Cu2O ALD film indicated nearly 1 at. % of carbon contamination and a phosphorous contamination below the detection limit after sputter cleaning. Systematic investigations of the reduction of Ru-doped Cu2O to metallic Cu by HCO2H or CO as reducing agents are described. Following the ALD of 3.0 nm Cu2O, the ultrathin films are reduced between 100 and 160 °C. The use of HCO2H at 110 °C enabled the reduction of around 90% Cu2O. HCO2H is found to be very effec...

Monolithic integration of focused 2D GMR spin valve magnetic field sensor for high-sensitivity (compass) applications (Presentation Recording)

We have designed and fabricated 2D GMR spin valve sensors on the basis of IrMn/CoFe/Cu/CoFe/NiFe nanolayers in monolithic integration for high sensitivity applications. For a maximum signal-to-noise ratio, we realize a focused double full bridge layout featuring an antiparallel exchange bias pinning for neighbouring meanders and an orthogonal pinning for different bridges. This precise alignment is achieved with microscopic precision by laser heating and subsequent in-field cooling. Striving for maximum signal sensitivity and minimum hysteresis, we study in detail the impact of single meander geometry on the total magnetic structure and electronic transport properties. The investigated geometrical parameters include stripe width, stripe length, cross bar material and total meander length. In addition, the influence of the relative alignment between reference magnetization (pinned layer) and shape anisotropy (free layer) is studied. The experimentally obtained data are moreover compared to the predictions of tailored micromagnetic simulations. Using a set of optimum parameters, we demonstrate that our sensor may readily be employed to measure small magnetic fields, such as the ambient (geomagnetic) field, in terms of a 2D vector with high spatial (~200 μm) and temporal (~1 ms) resolution.

Effects of annealing on the microstructural evolution of copper films using texture analysis

Successful copper investigation is a key for the newest technologies. Today copper becomes a more and more widespread material in interconnect technology. Its main advantages are a lower resistivity, high conductivity and high purity. Thin copper films were grown by electrodeposition on copper seed layers which were grown by MOCVD and PVD on different barrier layers such as MOCVD titanium-nitride and sputtered tantalum-nitride coated silicon wafers. The bulk copper films were then subjected to i) self-annealing at room temperature, ii) vacuum annealing and iii) N2 annealing at various temperatures periods of time.