Steffen Schulze

Model based mask process correction and verification for advanced process nodes

The extension of optical lithography at 193nm wavelength to the 32nm node and beyond drives advanced resolution enhancement techniques that impose even tighter tolerance requirements on wafer lithography and etch as well as on mask manufacturing. The presence of residual errors in photomasks and the limitations of capturing those in process models for the wafer lithography have triggered development work for separately describing and correcting mask manufacturing effects. Long range effects - uniformity and pattern loading driven - and short range effects - proximity and linearity - contribute to the observed signatures. The dominating source of the short range errors is the etch process and hence it was captured with a variable etch bias model in the past [1]. The paper will discuss limitations and possible extensions to the approach for improved accuracy. The insertion of mask process correction into a post tapeout flow imposes strict requirements for runtime and data integrity. The paper describes a comprehensive approach for mask process correction including calibration and model building, model verification, mask data correction and mask data verification. Experimental data on runtime performance is presented. Flow scenarios as well as other applications of mask process correction for gaining operational efficiency in both tapeout and mask manufacturing are discussed.

EUV mask-blank defect avoidance solutions assessment

It is anticipated that throughout the process development phase for the introduction of EUV lithography, defect free substrates won’t be available – even at the manufacturing stage, non-repairable defects may still be present. We investigate EDA-based approaches for defect avoidance, such as reticle floor planning, shifting the entire reticle field (pattern shift), pattern shift in addition to layout classification (smart shift), and defect repair in the data prior to mask write. This investigation is followed by an assessment of the complexity and impact on the mask manufacturing process of the various approaches. We then explore the results of experiments run using a software solution developed on the Calibre platform for EUV defect avoidance on various mask blanks, analyzing its effectiveness and performance.

Impact of 14-nm photomask uncertainties on computational lithography solutions

Abstract. Computational lithography solutions rely upon accurate process models to faithfully represent the imaging system output for a defined set of process and design inputs. These models rely upon the accurate representation of multiple parameters associated with the scanner and the photomask. Many input variables for simulation are based upon designed or recipe-requested values or independent measurements. It is known, however, that certain measurement methodologies, while precise, can have significant inaccuracies. Additionally, there are known errors associated with the representation of certain system parameters. With shrinking total critical dimension (CD) control budgets, appropriate accounting for all sources of error becomes more important, and the cumulative consequence of input errors to the computational lithography model can become significant. In this work, we examine via simulation the impact of errors in the representation of photomask properties including CD bias, corner rounding, refractive index, thickness, and sidewall angle. The factors that are most critical to be accurately represented in the model are cataloged. CD bias values are based on state-of-the-art mask manufacturing data, and other variable changes are speculated, highlighting the need for improved metrology and communication between mask and optical proxmity correction model experts. The simulations are done by ignoring the wafer photoresist model and show the sensitivity of predictions to various model inputs associated with the mask. It is shown that the wafer simulations are very dependent upon the one-dimensional/two-dimensional representation of the mask, and for three-dimensional, the mask sidewall angle is a very sensitive factor influencing simulated wafer CD results.

Assessment and comparison of different approaches for mask write time reduction

The extension of 193nm exposure wavelength to smaller nodes continues the trend of increased data complexity and subsequently longer mask writing times. We review the data preparation steps post tapeout, how they influence shot count as the main driver for mask writing time and techniques to reduce that impact. The paper discusses the application of resolution enhancements and layout simplification techniques; the fracture step and optimization methods; mask writing and novel ideas for shot count reduction. The paper will describe and compare the following techniques: optimized fracture, pre-fracture jog alignment, generalization of shot definition (L-shot), multi-resolution writing, optimized-based fracture, and optimized OPC output. The comparison of shot count reduction techniques will consider the impact of changes to the current state of the art using the following criteria: computational effort, CD control on the mask, mask rule compliance for manufacturing and inspection, and the software and hardware changes required to achieve the mask write time reduction. The paper will introduce the concepts and present some data preparation results based on process correction and fracturing tools.

Reducing shot count through optimization-based fracture

The increasing complexity of RET solutions with each new process node has increased the shot count of advanced photomasks. In particular, the introduction of inverse lithography masks represents a significant increase in mask complexity. Although shot count reduction can be achieved through careful management of the upstream OPC strategy and improvement of fracture algorithms, it is also important to consider more dramatic departures from traditional fracture techniques. Optimization based fracture allows for overlapping shots to be placed in a manner that allows the mask intent to be realized while achieving significant savings in shot count relative to traditional fracture based methods. We investigate the application of Optimization based fracture to reduce the shot count of inverse lithography masks, provide an assessment of the potential shot count savings, and assess its impact on lithography process window performance.

Pattern based mask process correction: impact on data quality and mask writing time

The continuous drive of the semiconductor industry towards smaller features sizes requires mask manufacturers to achieve ever tighter tolerances for the most critical dimensions on the mask. CD uniformity requires particularly tight control. Equipment manufacturers and process engineers target their development to support these requirements. But as numerous publications indicate, more sophisticated data correction methods are still employed to compensate for shortcomings in equipment and process or to account for the boundary conditions in some layouts that contribute to process deviations. Among the corrected effects are proximity and linearity effects, fogging and etch effects, and pattern fidelity. Different designs vary by pattern size distribution as well as by pattern density distribution. As the implementation of corrections for optical proximity effects in wafer lithography has shown, breaking up the original polygons in the design layout for selective and environment-aware correction yields increased data volumes and can have an impact on the data quality of the mask writing data. The paper investigates the effect of various correction algorithms specifically deployed for mask process effects on top of wafer process related corrections. The impact of MPC flows such as rule-based linearity and proximity correction and density-based long range effect correction on the metrics for data preparation and mask making is analyzed. Experimental data on file size, shot count and data quality indicators including small figure counts are presented for different correction approaches and a variety of correction parameters.

Illumination optimization effects on OPC and MDP

Illumination optimization has always been an important part of the process characterization and setup for new technology nodes. As we move to the 130nm node and beyond, this phase becomes even more critical due to the limited amount of available process window and the application of advanced model based optical proximity corrections (OPC). Illumination optimization has some obvious benefits in that it maximizes process latitude and therefore makes a process more robust to dose and focus variations that naturally occur during the manufacturing process. By mitigating the effect of process excursions, there are fewer numbers of reworks, faster cycle times and ultimately higher yield. Although these are the typical benefits associated with illumination optimization, there are also other potential benefits realized from an OPC modeling and mask data preparation (MDP) perspective as well. This paper will look into the not so obvious effects illumination optimization has on OPC and MDP. A fundamental process model built with suboptimal optical settings is compared against a model based on the optimal optical conditions. The optimal optical conditions will be determined based on simulations of the process window for several structures in a design using a metric of maximum common depth of focus (DOF) for a given minimum exposure latitude (EL). The amount of OPC correction will be quantified for both models and a comparison of OPC aggressiveness will be made. OPC runtimes will also be compared as well as output file size, amount of fragmentation, and the number of shot counts required in the mask making process. In conclusion, a summary is provided highlighting where OPC and MDP can benefit from proper illumination optimization.

High-performance fracturing for variable shaped beam mask writing machines

Mask manufacturing for the 100 and 65nm nodes is accompanied by an increasing deployment of VSB mask writing machines. The continuous integration trend in design and broad deployment of RET have a tremendous impact on file size and pattern complexity. The impact on the total turn-around time for a design is twofold: the time to get the data ready for the hand-off to the mask writer is growing but also the time it actually takes to write the mask is heavily influenced by the size and complexity of the data. Different parameters are measures of how the flow and the particular tooling impact both portions. The efficiency of the data conversion flow conducted by a software tool can be measured by the output file size, the scalability of the computing during parallel processing on multiple processors and the total cpu-time for the transformation. The mask writing of a particular data set is affected by the file size and the shot count. The latter one is the total amount of shots that are required to expose all patterns on the mask. The shot count can be estimated based on the figure count by type and their dimensions. The results of the fracturing have an impact on the mask quality -- in particular the grid size and the number and locations of small figures.

Advanced mask process modeling for 45-nm and 32-nm nodes

As tolerance requirements for the lithography process continue to shrink with each new technology node, the contributions of all process sequence steps to the critical dimension error budgets are being closely examined, including wafer exposure, resist processing, pattern etch, as well as the photomask process employed during the wafer exposure. Along with efforts to improve the mask manufacturing processes, the elimination of residual mask errors via pattern correction has gained renewed attention. The portfolio of correction tools for mask process effects is derived from well established techniques commonly used in optical proximity correction and in electron beam proximity effect compensation. The process component that is not well captured in the correction methods deployed in mask manufacturing today is etch. A mask process model to describe the process behavior and to capture the physical effects leading to deviation of the critical dimension from the target value represents the key component of model-based correction and verification. This paper presents the flow for generating mask process models that describe both shortrange and long-range mask process effects, including proximity loading effects from etching, pattern density loading effects, and across-mask process non-uniformity. The flow is illustrated with measurement data from real test masks. Application of models for both mask process correction and verification is discussed.

OASIS-based data preparation flows: progress report on containing data size explosion

The ever-increasing complexity of integrated circuits and their enabling process technology has accelerated the increase in data volume of post-RET data which is input to the photomask manufacturing industry. OASIS - the new stream format that has been developed by a working group under the sponsorship of the SEMI Data Path Task Force enables the representation of IC layout data in a much more compact form than GDSII and facilitates the incorporation of hierarchical data into the mask-making infrastructure. OASIS achieves on average a >10x reduction in file size compared to GDSII files and structures the data in a way, which allows a straightforward translation from a hierarchical format to the required flat mask perspective. Owing to the efficiency in representing the data, OASIS files are smaller than commonly used flat exchange formats - like MEBES, thus enabling an efficient hierarchical data flow both from the processing as well as the file handling prospective. The implementation of OASIS into post-tapeout data flows will be discussed and experimental results on OASIS-based data preparation flows will be shown.