Ramtin Zand

A Tunable Majority Gate-Based Full Adder Using Current-Induced Domain Wall Nanomagnets

Domain wall nanomagnet (DWNM)-based devices have been extensively studied as a promising alternative to the conventional CMOS technology in both the memory and logic implementations due to their non-volatility, near-zero standby power, and high integration density characteristics. In this paper, we leverage a physics-based model of a DWNM device to design a highly scalable current-mode majority gate to achieve a novel one bit full-adder (FA) circuit. The modeled DWNM specifications are calibrated with the experimentally measured data. The functionality of the proposed DWNM-based FA (DWNM-FA) is verified using a SPICE circuit simulator. The detailed analysis and the calculations have been performed to realize the proposed DWNM-FA delay and power consumption corresponding to the various induced input currents at different operating temperatures. The power-delay product of DWNM-FA is examined to tune the operation within the optimum induced input current region to obtain desired power-delay requirements over a range of 200 μA to 1 mA at temperatures from 298 to 378 K. Finally, the comparison results exhibit 52% and 49% area improvement as well as 41% and 31% improvement in device count complexity over CMOS-based and magnetic tunnel junction-based FA designs, respectively.

Scalable Adaptive Spintronic Reconfigurable Logic Using Area-Matched MTJ Design

Spin-transfer torque (STT) random access memory has been researched as a promising alternative for static random access memory in reconfigurable fabrics, particularly in lookup tables (LUTs), due to its nonvolatility, low standby and static power, and high integration density features. In this brief, we leverage physical characteristics of magnetic tunnel junctions (MTJs) to design a unique reference MTJ which has a calibrated resistance matching the STT-based LUT (STT-LUT) circuit requirements to provide optimal reading operation. Results obtained show 42% and 70% power-delay product (PDP) improvement over previous MTJ-based LUT designs. Moreover, a four-input adaptive STT-based LUT (A-LUT) is proposed based on the developed STT-LUT, which is configurable to function in seven independent modes. An n-input A-LUT exhibits PDP which can be a fraction of n-input STT-LUT PDP, when performing two-input to (n-1)-input Boolean logic functions.

Energy-Efficient Nonvolatile Reconfigurable Logic Using Spin Hall Effect-Based Lookup Tables

In this paper, we leverage magnetic tunnel junction (MTJ) devices to design an energy-efficient nonvolatile lookup table (LUT), which utilizes a spin Hall effect (SHE) assisted switching approach for MTJ storage cells. SHE–MTJ characteristics are modeled in Verilog-A based on precise physical equations. Functionality of the proposed SHE–MTJ-based LUT is validated using SPICE simulation. Our proposed SHE—MTJ-based LUT (SHE–LUT) is compared with the most energy-efficient MTJ-based LUT circuits. The obtained results show more than 6%, 37%, and 67% improvement over three previous MTJ-based designs in term of read energy consumption. Moreover, the reconfiguration delay and energy of the proposed design is compared with that of the MTJ-based LUTs which utilize the spin transfer torque (STT) switching approach for reconfiguration. The results exhibit that SHE–LUT can operate at 78% higher clock frequency while achieving at least 21% improvement in terms of reconfiguration energy consumption. The operation-specific clocking mechanisms for managing the SHE–LUT operations are introduced along with detailed analyses concerning tradeoffs. Results are extended to design a 6-input fracturable LUT using SHE–MTJs.

Reactive rejuvenation of CMOS logic paths using self-activating voltage domains

Although the trend of technology scaling is sought to realize higher performance computer systems, it also results in Integrated Circuits (ICs) suffering from increasing Process, Voltage, and Temperature (PVT) variations and adverse aging effects. In most cases, these reliability threats manifest themselves as timing errors on critical speed-paths of the circuit, if a large design guardband is not reserved. In this work, we propose the Reactive Rejuvenation (RR) architectural approach consisting of detection and recovery phases to mitigate circuit from BTI-induced aging. The BTI impact on the critical and near critical paths performance is continuously examined through a lightweight logic circuit which asserts an error signal in the case of any timing violation in those paths. By utilizing timing violation occurrence in the system, the timing-sensitive portion of the circuit is recovered from BTI through switching computations to redundant aging-critical voltage domain. The proposed technique achieves aging mitigation and reduced energy consumption as compared to a baseline circuit. Thus, significant voltage guardbands to meet the desired timing specification are avoided.

Energy-Efficient and Process-Variation-Resilient Write Circuit Schemes for Spin Hall Effect MRAM Device

In this paper, various energy-efficient write schemes are proposed for switching operation of spin hall effect (SHE)-based magnetic tunnel junctions (MTJs). A transmission gate (TG)-based write scheme is proposed, which provides a symmetric and energy-efficient switching behavior. We have modeled an SHE-MTJ using precise physics equations, and then leveraged the model in SPICE circuit simulator to verify the functionality of our designs. Simulation results show the TG-based write scheme advantages in terms of device count and switching energy. In particular, it can operate at 12% higher clock frequency while realizing at least 13% reduction in energy consumption compared to the most energy-efficient write circuits. We have analyzed the performance of the implemented write circuits in presence of process variation (PV) in the transistors’ threshold voltage and SHE-MTJ dimensions. Results show that the proposed TG-based design is the second most PV-resilient write circuit scheme for SHE-MTJs among the implemented designs. Finally, we have proposed the 1TG-1T-1R SHE-based magnetic random access memory (MRAM) bit cell based on the TG-based write circuit. Comparisons with several of the most energy-efficient and variation-resilient SHE-MRAM cells indicate that 1TG-1T-1R delivers reduced energy consumption with 43.9% and 10.7% energy-delay product improvement, while incurring low area overhead.

Adaptive Mitigation of Radiation-Induced Errors and TDDB in Reconfigurable Logic Fabrics

Self-reliance capabilities of mission-critical systems gain importance as technology scaling and logic capacity of SRAM-based reconfigurable devices increase. The Sustainable Modular Adaptive Redundancy Technique (SMART) is evaluated to optimize the reliability, availability, and energy efficiency of reconfigurable logic devices with a given area footprint. A Monte Carlo driven Continuous Markov Time Chain (CMTC) simulation is conducted to assess availability using runtime adaptation with SMART in comparison to conventional design-time static Triple Modular Redundancy (TMR) techniques. In harsh environments, adaptive redundancy is shown to improve system availability under lengthy repair times, and to a more significant degree under rapid recovery times. When compared to TMR, adaptive redundancy achieves power savings ranging from 22% to 29%, at a reduced area cost ranging from 17% to 24%, while maintaining comparable levels of availability.

Logic-Encrypted Synthesis for Energy-Harvesting-Powered Spintronic-Embedded Datapath Design

The objectives of advancing secure, intermittency-tolerant, and energy-aware logic datapaths are addressed herein by developing a spin-based design methodology and its corresponding synthesis steps. The approach selectively-inserts Non-Volatile (NV) Polymorphic Gates (PGs) to realize datapaths which are suitable for intrinsic operation in Energy-Harvesting-Powered (EHP) devices. Spin Hall Effect (SHE)-based Magnetic Tunnel (MTJs) are utilized to design NV-PGs, which are combined within a Flip-Flop (FF) circuit to develop a PG-FF realizing Boolean logic functions with inherent state-holding capability. The reconfigurability of PGs is leveraged for logic-encryption to enhance the security of the developed intermittency-resilient circuits, which are applied to ISCAS-89, MCNS, and ITC-99 benchmarks. The results obtained indicate that the PG-FF based design can achieve up to 7.1% and 13.6% improvements in terms of area and Power Delay Product (PDP), respectively, compared to NV-FF based methodologies that replace the CMOS-based FFs with NV-FFs. Further PDP improvements are achieved by using low-energy barrier SHE-MTJ devices within the PG-FF circuit. SHE-MTJs with 30kT energy exhibit 40.5% reduction in PDP at the cost of lower retention times in the range of minutes, which is still sufficient to achieve forward progress in EHP devices having more than hundreds of power-on and power-off cycles per minute.

Low-Energy Deep Belief Networks Using Intrinsic Sigmoidal Spintronic-based Probabilistic Neurons

A resistive deep belief network (R-DBN) architecture is developed using the physics of nanomagnets to provide a natural hardware representation for individual probabilistic neurons. Probabilistic spin logic devices (p-bits) are modeled to demonstrate a sigmoidal activation function. A hybrid CMOS/spin based weighted array structure is designed to implement a restricted Boltzmann machine (RBM). Device-level simulations based on precise physics relations are used to validate the sigmoidal relation between the output probability of a p-bit and its input currents. Characteristics of the resistive networks and p-bits are modeled in SPICE to perform a circuit-level simulation, which investigates the performance, area, and power consumption tradeoffs of the weighted array. In the application-level simulation, an R-DBN is implemented in MATLAB for digit recognition using the extracted device and circuit behavioral models. The MNIST data set is used to assess the accuracy of the R-DBN using 100 to 5,000 training images for five distinct network topologies. The results indicate that a baseline error rate of 36.8% for a 784x10 R-DBN trained by 100 samples can be reduced to only 3.7% using a 784x800x800x10 R-DBN trained by 5,000 input samples. Finally, power dissipation and accuracy tradeoffs for probabilistic computing mechanisms using resistive devices are identified.A low-energy hardware implementation of deep belief network (DBN) architecture is developed using near-zero energy barrier probabilistic spin logic devices (p-bits), which are modeled to realize an intrinsic sigmoidal activation function. A CMOS/spin based weighted array structure is designed to implement a restricted Boltzmann machine (RBM). Device-level simulations based on precise physics relations are used to validate the sigmoidal relation between the output probability of a p-bit and its input currents. Characteristics of the resistive networks and p-bits are modeled in SPICE to perform a circuit-level simulation investigating the performance, area, and power consumption tradeoffs of the weighted array. In the application-level simulation, a DBN is implemented in MATLAB for digit recognition using the extracted device and circuit behavioral models. The MNIST data set is used to assess the accuracy of the DBN using 5,000 training images for five distinct network topologies. The results indicate that a baseline error rate of 36.8% for a 784x10 DBN trained by 100 samples can be reduced to only 3.7% using a 784x800x800x10 DBN trained by 5,000 input samples. Finally, Power dissipation and accuracy tradeoffs for probabilistic computing mechanisms using resistive devices are identified.

Heterogeneous energy-sparing reconfigurable logic: spin-based storage and CNFET-based multiplexing

Field programmable gate array (FPGA) attributes of logic configurability, bitstream storage, and dynamic signal routing can be realised by leveraging the complementary benefits of emerging devices with complementary metal oxide semiconductor (CMOS)-based devices. A novel carbon/magnet lookup table (CM-LUT) is developed and evaluated by trading off a range of mixed heterogeneous technologies to balance energy, delay, and reliability attributes. Herein, magnetic spintronic devices are employed in the configuration memory to contribute non-volatility and high scalability. Meanwhile, carbon nanotube field-effect transistors (CNFETs) provide desirable conductivity, low delay, and low power consumption. The proposed CM-LUT offers ultra-low power and high-speed operation while maintaining high endurance re-programmability with increased radiation-induced soft-error immunity. The proposed four-input one-output CM-LUT utilises 41 CNFETs and 20 magnetic tunnel junctions for read operations and 35 CNFET to perform write operations. Results indicate that CM-LUT achieves an average four-fold energy reduction, eight-fold faster circuit operation and 9.3% reconfiguration power delay product improvement in comparison with spin-based look-up tables. Finally, additional hybrid technology designs are considered to balance performance with the demands of energy consumption for near-threshold operation.