Arman Roohi

Design and evaluation of an ultra-area-efficient fault-tolerant QCA full adder

Quantum-dot cellular automata (QCA) has been studied extensively as a promising switching technology at nanoscale level. Despite several potential advantages of QCA-based designs over conventional CMOS logic, some deposition defects are probable to occur in QCA-based systems which have necessitated fault-tolerant structures. Whereas binary adders are among the most frequently-used components in digital systems, this work targets designing a highly-optimized robust full adder in a QCA framework. Results demonstrate the superiority of the proposed full adder in terms of latency, complexity and area with respect to previous full adder designs. Further, the functionality and the defect tolerance of the proposed full adder in the presence of QCA deposition faults are studied. The functionality and correctness of our design is confirmed using high-level synthesis, which is followed by delineating its normal and faulty behavior using a Probabilistic Transfer Matrix (PTM) method. The related waveforms which verify the robustness of the proposed designs are discussed via generation using the QCADesigner simulation tool.

A Tunable Majority Gate-Based Full Adder Using Current-Induced Domain Wall Nanomagnets

Domain wall nanomagnet (DWNM)-based devices have been extensively studied as a promising alternative to the conventional CMOS technology in both the memory and logic implementations due to their non-volatility, near-zero standby power, and high integration density characteristics. In this paper, we leverage a physics-based model of a DWNM device to design a highly scalable current-mode majority gate to achieve a novel one bit full-adder (FA) circuit. The modeled DWNM specifications are calibrated with the experimentally measured data. The functionality of the proposed DWNM-based FA (DWNM-FA) is verified using a SPICE circuit simulator. The detailed analysis and the calculations have been performed to realize the proposed DWNM-FA delay and power consumption corresponding to the various induced input currents at different operating temperatures. The power-delay product of DWNM-FA is examined to tune the operation within the optimum induced input current region to obtain desired power-delay requirements over a range of 200 μA to 1 mA at temperatures from 298 to 378 K. Finally, the comparison results exhibit 52% and 49% area improvement as well as 41% and 31% improvement in device count complexity over CMOS-based and magnetic tunnel junction-based FA designs, respectively.

Scalable Adaptive Spintronic Reconfigurable Logic Using Area-Matched MTJ Design

Spin-transfer torque (STT) random access memory has been researched as a promising alternative for static random access memory in reconfigurable fabrics, particularly in lookup tables (LUTs), due to its nonvolatility, low standby and static power, and high integration density features. In this brief, we leverage physical characteristics of magnetic tunnel junctions (MTJs) to design a unique reference MTJ which has a calibrated resistance matching the STT-based LUT (STT-LUT) circuit requirements to provide optimal reading operation. Results obtained show 42% and 70% power-delay product (PDP) improvement over previous MTJ-based LUT designs. Moreover, a four-input adaptive STT-based LUT (A-LUT) is proposed based on the developed STT-LUT, which is configurable to function in seven independent modes. An n-input A-LUT exhibits PDP which can be a fraction of n-input STT-LUT PDP, when performing two-input to (n-1)-input Boolean logic functions.

Towards ultra-efficient QCA reversible circuits

Nanotechnologies, remarkably Quantum-dot Cellular Automata (QCA), offer an attractive perspective for future computing technologies. In this paper, QCA is investigated as an implementation method for reversible logic. A novel XOR gate and also a new approach to implement 2:1 multiplexer are presented. Moreover, an efficient and potent universal reversible gate based on the proposed XOR gate is designed. The proposed reversible gate has a superb performance in implementing the QCA standard benchmark combinational functions in terms of area, complexity, power consumption, and cost function in comparison to the other reversible gates. The gate achieves the lowest overall cost among the most cost-efficient designs presented so far, with a reduction of 24%. In order to employ the merits of reversibility, the proposed reversible gate is leveraged to design the four common latches (D latch, T latch, JK latch, and SR latch). Specialized structures of the proposed circuits could be used as building blocks in designing sequential and combinational circuits in QCA architectures.

Design and Verification of New n-Bit Quantum-Dot Synchronous Counters Using Majority Function-Based JK Flip-Flops

Quantum-dot Cellular Automata (QCA) is an attractive nanoelectronics paradigm which is widely advocated as a possible replacement of conventional CMOS technology. Designing memory cells is a very i...

Energy-Efficient Nonvolatile Reconfigurable Logic Using Spin Hall Effect-Based Lookup Tables

In this paper, we leverage magnetic tunnel junction (MTJ) devices to design an energy-efficient nonvolatile lookup table (LUT), which utilizes a spin Hall effect (SHE) assisted switching approach for MTJ storage cells. SHE–MTJ characteristics are modeled in Verilog-A based on precise physical equations. Functionality of the proposed SHE–MTJ-based LUT is validated using SPICE simulation. Our proposed SHE—MTJ-based LUT (SHE–LUT) is compared with the most energy-efficient MTJ-based LUT circuits. The obtained results show more than 6%, 37%, and 67% improvement over three previous MTJ-based designs in term of read energy consumption. Moreover, the reconfiguration delay and energy of the proposed design is compared with that of the MTJ-based LUTs which utilize the spin transfer torque (STT) switching approach for reconfiguration. The results exhibit that SHE–LUT can operate at 78% higher clock frequency while achieving at least 21% improvement in terms of reconfiguration energy consumption. The operation-specific clocking mechanisms for managing the SHE–LUT operations are introduced along with detailed analyses concerning tradeoffs. Results are extended to design a 6-input fracturable LUT using SHE–MTJs.

Reactive rejuvenation of CMOS logic paths using self-activating voltage domains

Although the trend of technology scaling is sought to realize higher performance computer systems, it also results in Integrated Circuits (ICs) suffering from increasing Process, Voltage, and Temperature (PVT) variations and adverse aging effects. In most cases, these reliability threats manifest themselves as timing errors on critical speed-paths of the circuit, if a large design guardband is not reserved. In this work, we propose the Reactive Rejuvenation (RR) architectural approach consisting of detection and recovery phases to mitigate circuit from BTI-induced aging. The BTI impact on the critical and near critical paths performance is continuously examined through a lightweight logic circuit which asserts an error signal in the case of any timing violation in those paths. By utilizing timing violation occurrence in the system, the timing-sensitive portion of the circuit is recovered from BTI through switching computations to redundant aging-critical voltage domain. The proposed technique achieves aging mitigation and reduced energy consumption as compared to a baseline circuit. Thus, significant voltage guardbands to meet the desired timing specification are avoided.

Loss-Aware Switch Design and Non-Blocking Detection Algorithm for Intra-Chip Scale Photonic Interconnection Networks

As the number of on-chip processor cores increases, power-efficient solutions are sought for data communication between cores. The Helix-h non-blocking photonic switch is developed to improve physical-layer and network performance parameters for a wide range of silicon nano-photonic multicore interconnection topologies. Traffic benchmarks and practical case studies using a cycle-accurate simulation environment indicate significantly reduced insertion loss providing improved bandwidth density and scalability to manycore plurality. Improvements in system performance parameters are quantified for network bandwidth, transmission efficiency, and latency in popular photonic internconnection topologies, in comparison to previous switch designs. For instance, utilizing the Helix-h switch in a mesh topology, the bandwidth is increased by 112 percent compared to the previously highest performing switch design. Execution time and energy efficiency are improved by up to 92 and 99 percent, respectively, for representative multicore applications. Finally, the technique is generalized to a novel graph-theoretic method for articulating blocking conditions in photonic switches.

Cost-efficient QCA reversible combinational circuits based on a new reversible gate

Nanotechnologies, notably Quantum-dot Cellular Automata (QCA), provide an attractive perspective for future computing technologies. In this paper, Quantum-dot Cellular Automata (QCA) is investigated as an implementation method for reversible logic. A novel XOR gate and also a new approach to implement 2:1 multiplexer are presented. Moreover, an efficient and potent universal reversible gate based on the proposed XOR gate is designed. The proposed reversible gate has a superb performance in implementing the QCA standard benchmark combinational functions in terms of area, complexity, power consumption and cost function in comparison to the other reversible gates. The gate achieves the lowest overall cost among the most cost-efficient designs presented so far, with a reduction of 24%.

Implementation of reversible logic design in nanoelectronics on basis of majority gates

Due to low power dissipation in computing, reversible logic is an attractive field of research in quantum and optical computing. Since the conventional CMOS technology cannot be used for implementing reversible gates owing to its high power dissipation, employing novel technologies such as nano-scale ones are being deployed. In this paper we utilize Quantum-dot Cellular Automata (QCA) as a candidate technology for implementing reversible logic gates. This paper presents a new realization approach to reversible logic based on majority gates (MGs) and a new reversible gate is proposed as well. The gate will be compared with an existing MG-based structure in terms of delay, complexity and area. The results show that even though our gate requires more cells, it returns the outputs in less clock cycles and hence the design is faster.