Randy Morris

Exploring the Design of 64- and 256-Core Power Efficient Nanophotonic Interconnect

High-performance and low-power network-on-chips (NoCs) will be required to support the increasing number of cores in future chip multiprocessors. In this paper, we propose a scalable low-power 64-core NoC design called PROPEL that uses emerging nanophotonic technology. PROPEL strikes a balance between cheaper electronics and more expensive optics by facilitating nanophotonic interconnects for long distance interrouter communication and electrical switching for routing and flow control. In addition, PROPEL reduces the number of required components by facilitating communication in both the x- and y-directions. We also propose a 256-core scaled version of PROPEL called E-PROPEL that uses four separate PROPEL networks connected together by an optical crossbar. We also propose two different optical crossbar implementations using single and double microring resonators, where the single microring design has minimal optical losses (-4.32 dB) and the double microring design has minimal area overhead (0.0576 mm2). We have simulated both PROPEL and E-PROPEL using synthetic and SPLASH-2 traffic, where our results indicate that PROPEL and E-PROPEL significantly reduce power (tenfold) and increase performance (twofold) over other well-known electrical networks.

Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance

As power dissipation in future Networks-on-Chips (NoCs) is projected to be a major bottleneck, researchers are actively engaged in developing alternate power-efficient technology solutions. Photonic interconnects is a disruptive technology solution that is capable of delivering the communication bandwidth at low power dissipation when the number of cores is scaled to large numbers. Similarly, 3D stacking is another interconnect technology solution that can lead to low energy/bit for communication. In this paper, we propose to combine photonic interconnects with 3D stacking to develop a scalable, reconfigurable, power-efficient and high-performance interconnect for future many-core systems, called R-3PO (Reconfigurable 3DPhotonic Networks-on-Chip). We propose to develop a multi-layer photonic interconnect that can dynamically reconfigure without system intervention and allocate channel bandwidth from less utilized links to more utilized communication links. In addition to improving performance, reconfiguration can re-allocate bandwidth around faulty channels, thereby increasing the resiliency of the architecture and gracefully degrading performance. For 64-core reconfigured network, our simulation results indicate that the performance can be further improved by 10%-25% for Splash-2, PARSEC and SPEC CPU2006 benchmarks, where as simulation results for 256-core chip indicate a performance improvement of more than 25% while saving 6%-36% energy when compared to state-of-the-art on-chip electrical and optical networks.

Three-Dimensional Stacked Nanophotonic Network-on-Chip Architecture with Minimal Reconfiguration

As throughput, scalability, and energy efficiency in network-on-chips (NoCs) are becoming critical, there is a growing impetus to explore emerging technologies for implementing NoCs in future multicore and many-core architectures. Two disruptive technologies on the horizon are nanophotonic interconnects (NIs) and 3D stacking. NIs can deliver high on-chip bandwidth while delivering low energy/bit, thereby providing a reasonable performance-per-watt in the future. Three-dimensional stacking can reduce the interconnect distance and increase the bandwidth density by incorporating multiple communication layers. In this paper, we propose an architecture that combines NIs and 3D stacking to design an energy-efficient and reconfigurable NoC. We quantitatively compare the hardware complexity of the proposed topology to other nanophotonic networks in terms of hop count, network diameter, radix, and photonic parameters. To maximize performance, we also propose an efficient reconfiguration algorithm that dynamically reallocates channel bandwidth by adapting to traffic fluctuations. For 64-core reconfigured network, our simulation results indicate that the execution time can be reduced up to 25 percent for Splash-2, PARSEC, and SPEC CPU2006 benchmarks. Moreover, for a 256-core version of the proposed architecture, our simulation results indicate a throughput improvement of more than 25 percent and energy savings of 23 percent on synthetic traffic when compared to competitive on-chip electrical and optical networks.

Power-Efficient and High-Performance Multi-level Hybrid Nanophotonic Interconnect for Multicores

Network-on-Chips (NoCs) are becoming the defacto standard for interconnecting the increasing number of cores in chip multiprocessors (CMPs) by overcoming the scalability and wire delay problems of shared buses. However, recent research has shown that future NoCs will be limited by power dissipation and reduced performance forcing architects to explore other technologies that are complementary metal oxide semiconductor (CMOS) compatible. In this paper, we propose ET-PROPEL (Extended Token based Photonic Reconfigurable On-Chip Power and Area-Efficient Links) architecture to utilize the emerging nanophotonic technology to design a high-bandwidth, low latency and low power multi-level hybrid interconnect that balances cost and performance. We develop our interconnect at three levels: at the first level (x) we design a fully connected network for exploiting locality; at the second level(y), we design a shared channel using optical tokens to reduce power while providing full connectivity and at the third level (z), we propose a novel nanophotonic crossbar that provides scalable bisection bandwidth. The first two levels are combined into T-PROPEL(token-PROPEL, 64 cores) and four separate T-PROPELs are combined into ET-PROPEL (256 cores). We have simulated both T-PROPEL and ET-PROPEL using synthetic and SPLASH-2 traffic, where our results indicate that T-PROPEL and ET-PROPEL significantly reduce power(10-fold) and increase performance (3-fold) over other well known electrical and photonic networks.

3D-NoC: Reconfigurable 3D photonic on-chip interconnect for multicores

The power dissipation of metallic interconnects in future multicore architectures is projected to be a major bottleneck as we scale to sub-nanometer regime. This has motivated researchers to develop alternate power-efficient technology solutions to the performance limitations of future multicores. Nanophotonic interconnects (NIs) is a disruptive technology solution that is capable of delivering the communication bandwidth at low power dissipation when the number of cores is scaled to large numbers. Similarly, 3D stacking is another interconnect technology solution that can lead to low energy/bit for communication. In this paper, we propose to combine NIs with with 3D stacking to develop a scalable, reconfigurable, power-efficient and high-performance interconnect for future many-core systems called 3D-NoC. We propose to develop a multi-layer NIs that can dynamically reconfigure without system intervention and allocate channel bandwidth from less utilized links to more utilized communication links. Our simulation results indicate that the performance can be further improved by 10%-25% for Splash-2, PARSEC and SPEC CPU2006 benchmarks.

Extending the Energy Efficiency and Performance With Channel Buffers, Crossbars, and Topology Analysis for Network-on-Chips

Network-on-chips (NoCs) have emerged as a scalable solution to the wire delay constraints, thereby providing a high-performance communication fabric for future multicores. Research has shown that power, area, and performance of the NoC architecture are tightly integrated with the design and optimization of the link, router (buffer and crossbar), and topology. Recent work has shown that adaptive channel buffers (on-link storage) can considerably reduce power consumption and area overhead by reducing or replacing the power-hungry router buffers. However, channel buffer design can lead to head-of-line (HoL) blocking, which eventually reduces the throughput of the network. In this paper, we design channel buffers and router crossbars to improve the performance (latency, throughput) while reducing the power consumption. In addition, we implement the proposed channel buffers and crossbar organizations in a concentrated torus (CTorus) topology which is a dual network without the additional area overhead. We compare other dual networks with leading topologies such as mesh2X, concentrated mesh2X (CMesh2X), and flattened butterfly2X (FBfly2X), each implemented with channel buffers. Our proposed designs analyze the power-performance-area tradeoff in designing channel buffers for NoC architectures while alleviating HoL blocking through buffer organizations and crossbar optimizations. Results using Synopsys design compiler showed that the buffer and crossbar organizations for an 8 × 8 mesh architecture can reduce power consumption by 25%-40%, improve throughput and reduce latency by 525%, while occupying 4%-13% more area when compared to the baseline architecture for both synthetic as well as real benchmark traces such as Princeton Application Repository for Shared-Memory Computers (PARSEC) and Standard Performance Evaluation Corporation (SPEC). CPU2006. When the energy-efficient buffer and crossbar organization was inserted into our CTorus topology, we further reduced energy dissipation by 32% and area by 53%, on average, over mesh2X, CMesh2X, and FBfly2X.

Design of a performance enhanced and power reduced dual-crossbar Network-on-Chip (NoC) architecture

The input buffers of the current packet-switched Network-on-Chip (NoC) architectures consume a significant portion of the total power of the interconnection network. Reducing the size of input buffers would result in degraded performance, while eliminating all buffers would result in increased power at high network load. In this article, we propose DXbar: an innovative dual-crossbar design. By combining the advantages of buffered and bufferless networks, we achieve at least 20% performance improvement in terms of throughput and latency, and at least 20% power saving over buffered networks with virtual channels. Furthermore, DXbar can outperform current bufferless networks with deflecting and dropping protocols while consuming at most half of the power.

On-Chip photonic interconnects for scalable multi-core architectures

In this paper, we propose PROPEL, a photonic network-on-chip (NoC) that improves performance and power with energy-efficient opto-electronic components for future chip multiprocessors (CMPs). Our analytical and simulation results indicate that PROPEL improves throughput and reduces power over optical and electrical networks for various traffic traces while requiring fewer photonic components and devices.

Co-design of channel buffers and crossbar organizations in NoCs architectures

Network-on-Chips (NoCs) have emerged as a scalable solution to the wire delay constraints, thereby providing a high-performance communication fabric for future multicores. Research has shown that power, area and performance of Network-on-Chips (NoCs) architecture are tightly integrated with the design and optimization of the link and router (buffer and crossbar). Recent work has shown that adaptive channel buffers (on-link storage) can considerably reduce power consumption and area overhead by reducing or replacing the power hungry router buffers. However, channel buffer design can lead to Head-of-Line (HoL) blocking which eventually reduces the throughput of the network. In this paper, we explore the design space of organizing channel buffers and router crossbars to improve the performance (latency, throughput) while reducing the power consumption. Our proposed designs analyze the power-performance-area trade-off in designing channel buffers for NoC architectures while overcoming HoL blocking through crossbar optimizations. Our simulation and NoC design synthesis shows that for a 8 × 8 mesh architecture, we can reduce the power consumption by 25–40%, improve performance by 10–25% while occupying 4–13% more area when compared to the baseline architecture.

Design of on-chip networks using microring-resonator based nanophotonic crossbar for future multicores

We propose a microring resonator based nanophotonic crossbar to implement a 256-core network-on-chip architecture called E-PROPEL. Our results indicate E-PROPEL consumes 3× less power and increases performance by 2× when compared to leading electrical networks.