Raqibul Hasan

Exploring the design space of specialized multicore neural processors

This study examines the design of several novel specialized multicore neural processors. Systems based on SRAM cores and memristor devices were examined. Detailed circuit simulations were used to ensure that the systems could be compared accurately. Two types of memristor cores were examined: digital and analog cores. Novel circuits were designed for both of these memristor systems. Additionally full system evaluation of multicore processors based on these cores and specialized routing circuits were developed. Our results show that the memristor systems yield the highest throughput and lowest power. We compared these specialized systems to more traditional HPC systems. Two commodity high performance processors were examined: a six core Intel Xeon processor, and an NVIDIA Tesla M2070 GPGPU. Care was taken to ensure the code on each platform was very efficient (multi-threaded on the Xeon processor, and a high device utilization CUDA program on the GPGPU). Our results indicate that the specialized systems can be between two to five orders more energy efficient compared to the traditional HPC systems. Additionally the specialized cores take up much less die area - allowing in some cases a reduction from 179 Xeon six-core processor chips to 1 memristor based multicore chip and a corresponding reduction in power from 17 kW down to 0.07 W.

Enabling back propagation training of memristor crossbar neuromorphic processors

Recent studies have shown that memristor crossbar based neuromorphic hardware enables high performance implementations of neural networks at low power and in low chip area. This paper presents circuits to train a cascaded set of memristor crossbars representing a multi-layered neural network. The circuits presented implement back-propagation training and would enable on-chip training of memristor crossbars. On-chip training of memristor crossbars can be necessary to overcome the effect of device variability and alternate current paths within crossbars being used as neural networks. We model the memristor crossbars in SPICE in order capture alternate current paths and the impact of wire resistance. Our design can be scaled to multiple neural layers and multiple output neurons. We demonstrate the training of up to three layered neural networks evaluating non-linearly separable functions through detailed SPICE simulations. This is the first study in the literature we have seen that examines the implementation of back-propagation based training of memristor crossbar circuits. The impact of this work would be to enable the design of highly energy efficient and compact neuromorphic processing systems that can be trained to implement large deep networks (such as deep belief networks).

Memristor crossbar based multicore neuromorphic processors

This paper describes memristor-based neuromorphic circuits for non-linear separable pattern recognition. We initially describe a memristor based neuron circuit and then show how multilayer neural networks can be constructed based on this neuron circuit. By applying neural network learning algorithms to these circuits, we demonstrate the learning of both linearly and non-linearly separable logic functions. The simulations are carried out in SPICE using a detailed memristor model so that the crossbar is simulated as accurately as possible. We also examine the system level performance of multicore memristor crossbar based neuromorphic processors. We consider the impact on on-chip routing, calculate the chip areas, and evaluate the timing of the systems in the study. The results indicate that such architectures can enable over 300,000 times energy efficiencies over traditional high performance computing architectures when processing large neural networks.

Hybrid crossbar architecture for a memristor based cache

This paper describes a new memristor crossbar architecture that is proposed for use in a high density cache design. This design has less than 10% of the write energy consumption than a simple memristor crossbar. Also, it has up to 3 times the bit density of an STT-MRAM system and up to 11 times the bit density of an SRAM architecture. The proposed architecture is analyzed using a detailed SPICE analysis that accounts for the resistance of the wires in the memristor structure. Additionally, the memristor model used in this work has been matched to specific device characterization data to provide accurate results in terms of energy, area, and timing. The proposed memory system was analyzed by modeling two different devices that vary in resistance range and switching time. This system does not require that the memristor devices have inherent diode effects which limit alternate current paths. Therefore this system is capable of utilizing a much broader class of devices.An architectural analysis has also been completed that shows how the memory system may perform as a cache memory. A hybrid cache structure was used to alleviate the long write latencies of memristor devices. This approach consisted of the tag array being made of SRAM cells while the data array was made of the memristor circuit proposed. This hybrid scheme allows multiple reads and writes to concurrently access different sub-arrays within a cache. The performance of these novel memristor based caches was compared to SRAM and STT-MRAM based caches through detailed simulations. The results show that the memristor caches are denser and allow better performance along with lower system power when compared to the STT-MRAM and SRAM caches.

Smart-TV Based Integrated E-health Monitoring System with Agent Technology

An ageing population is now the leading concern for higher healthcare costs due to more cases of chronic illnesses. Telemedicine systems based on modern Information and Communication Technology (ICT) are expected to play a pivotal role in alleviating the pressure on health care services. Environmental factors have also profound impact on health condition of the patients. As a consequence monitoring of human health along with the environmental (where the patient is located) health enables the health care providers to comprehend more accurately about a patients situation. In this paper we describe a novel integrated tele-monitoring framework (theoretical architecture) proposed to support both of the above functions simultaneously though a single framework. The proposed system also innovatively harnesses the power of emerging Smart-TV technology as a means of interaction between patient and the health care providers. To the best of our knowledge, this is the first of its kind.

Memristor based neuromorphic circuit for ex-situ training of multi-layer neural network algorithms

This paper describes a novel memristor-based neuromorphic circuit that can be used for ex-situ training of multi-layer neural network algorithms. The presented ex-situ programming technique can be used to map many key neural algorithms directly onto the grid of resistances in a memristor crossbar. This is possible because the proposed circuit is capable of calculating a true dot product. Existing circuits provide an approximated dot product based on a summation of conductance values, which is inaccurate due to the parallel structure of the crossbar. To show the effectiveness and versatility of this circuit, three different powerful neural networks were simulated. These include a Restricted Boltzmann Machine (RBM) for character recognition, a Convolutional Neural Network (CNN) also for character recognition, and a Multilayer Perceptron (MLP) trained to perform Sobel edge detection. Finally, an architecture analysis was performed showing that neuromorphic processors based on these memristor crossbar circuits can be up to 5 orders of magnitude more power efficient than a RISC processor.

Hybrid crossbar architecture for a memristor based memory

This paper describes a new memristor crossbar architecture that is proposed for use in a high density cache design. This design has less than 10% of the write energy consumption than a simple memristor crossbar. Also, it has up to 4 times the bit density of an STT-MRAM system and up to 11 times the bit density of an SRAM architecture. The proposed architecture is analyzed using a detailed SPICE analysis that accounts for the resistance of the wires in the memristor structure. Additionally, the memristor model used in this work has been matched to specific device characterization data to provide accurate results in terms of energy, area, and timing.

SPICE analysis of dense memristor crossbars for low power neuromorphic processor designs

This paper provides an analysis of neuromorphic circuits that are capable of learning logic functions. In this paper the training simulations are carried out in SPICE. Our simulations capture low level circuit functionality within the memristor crossbars as well as wire resistances between memristors. This is essential when properly modeling crossbar circuits. Wire resistances, wire capacitances, output comparators, and the number of data inputs are all investigated in this paper to show how these may impact a larger neuromorphic crossbar. Furthermore, it was shown that neural networks can properly train the passive memristor-based crossbars without having to use virtual ground mode operational amplifiers as suggested in previous work. This reduces the number of transistors required by the circuit by about 3 times and reduces the circuit power consumption by about 50 times when compared to the virtual ground design. The key impact of this study is the demonstration through low level circuit simulations that dense memristor crossbars can be effectively utilized to build neuromorphic processors.

Efficacy of memristive crossbars for neuromorphic processors

This paper describes memristor-based neuromorphic circuits for non-linear separable pattern recognition. We initially describe a memristor based neuron circuit and then show how multilayer neural networks can be constructed using this neuron circuit. These neuromorphic circuits are capable of learning both linearly and non-linearly separable logic functions. This paper presents the first study of applying neural network learning algorithms to these circuits in SPICE. Our simulations capture alternate current paths within the memristor crossbars and wire resistances that are essential to properly model in crossbar circuits. Our results show that neural network learning algorithms are able to train around these alternate current paths. Further, it was shown that neural networks can properly train the passive memristor-based crossbars without having to use virtual ground mode operational amplifiers as suggested in previous work. Our circuit requires in-situ training, but reduces the number of transistors required by the circuit by about 3 times and reduced the circuit power consumption almost 2 orders of magnitude compared to a virtual ground approach. The key impact of this study is the demonstration through low level circuit simulations that dense memristor crossbars can be effectively utilized to build neuromorphic processors.

Ex-situ training of dense memristor crossbar for neuromorphic applications

This study proposes a technique for programming a dense memristor crossbar array without isolation transistors (0T1M) in order to achieve ex-situ training of a neural network. Programming memristors to a specific resistance level requires an iterative process needing the reading of individual memristor resistances due to memristor device stochasticity. This paper presents a circuit to read individual resistances from a 0T1M crossbar and a method to map neuron synaptic weights into a novel neural circuit to enable ex-situ training. The results show that we are able to train the resistances in a 0T1M crossbar and that the 0T1M system is about 93% smaller in area than 1T1M systems.