Chris Yakopcic

A Memristor Device Model

This letter proposes a new mathematical model for memristor devices. It builds on existing models and is correlated against several published device characterizations. This letter identifies significant discrepancies between the existing models and published device characterization data. The proposed model addresses these discrepancies. In particular, it allows modeling of memristor-based neuromorphic systems.

Generalized Memristive Device SPICE Model and its Application in Circuit Design

This paper presents a SPICE model for memristive devices. It builds on existing models and is correlated against several published device characterization data with an average error of 6.04%. When compared to existing alternatives, the proposed model can more accurately simulate a wide range of published memristors. The model is also tested in large circuits with up to 256 memristors, and was less likely to cause convergence errors when compared to other models. We show that the model can be used to study the impact of memristive device variation within a circuit. We examine the impact of nonuniformity in device state variable dynamics and conductivity on individual memristors as well as a four memristor read/write circuit. These studies show that the model can be used to predict how variation in a memristor wafer may impact circuit performance.

Memristor SPICE model and crossbar simulation based on devices with nanosecond switching time

This paper presents a memristor SPICE model that is able to reproduce current-voltage relationships of previously published memristor devices. This SPICE model shows a stronger correlation to various published device data when compared to existing SPICE models. Furthermore, switching characteristics of published memristor devices with switching times in the nanosecond scale were modeled. Therefore, this model can be used to accurately simulate neural systems based on these high-speed memristors. This paper also demonstrates how this model can be used to accurately calculate switching energy of these high-speed devices, leading to more accurate power calculations in memristor based neural systems. Memristor crossbar circuits provide a potential method for developing very high density neural classifiers. This model was able to simulate crossbar circuits containing up to 256 memristors. It is significantly less likely to cause convergence errors when operating in the nanosecond switching regime with a large number of devices when compared with existing SPICE models.

Exploring the design space of specialized multicore neural processors

This study examines the design of several novel specialized multicore neural processors. Systems based on SRAM cores and memristor devices were examined. Detailed circuit simulations were used to ensure that the systems could be compared accurately. Two types of memristor cores were examined: digital and analog cores. Novel circuits were designed for both of these memristor systems. Additionally full system evaluation of multicore processors based on these cores and specialized routing circuits were developed. Our results show that the memristor systems yield the highest throughput and lowest power. We compared these specialized systems to more traditional HPC systems. Two commodity high performance processors were examined: a six core Intel Xeon processor, and an NVIDIA Tesla M2070 GPGPU. Care was taken to ensure the code on each platform was very efficient (multi-threaded on the Xeon processor, and a high device utilization CUDA program on the GPGPU). Our results indicate that the specialized systems can be between two to five orders more energy efficient compared to the traditional HPC systems. Additionally the specialized cores take up much less die area - allowing in some cases a reduction from 179 Xeon six-core processor chips to 1 memristor based multicore chip and a corresponding reduction in power from 17 kW down to 0.07 W.

Memristor crossbar based multicore neuromorphic processors

This paper describes memristor-based neuromorphic circuits for non-linear separable pattern recognition. We initially describe a memristor based neuron circuit and then show how multilayer neural networks can be constructed based on this neuron circuit. By applying neural network learning algorithms to these circuits, we demonstrate the learning of both linearly and non-linearly separable logic functions. The simulations are carried out in SPICE using a detailed memristor model so that the crossbar is simulated as accurately as possible. We also examine the system level performance of multicore memristor crossbar based neuromorphic processors. We consider the impact on on-chip routing, calculate the chip areas, and evaluate the timing of the systems in the study. The results indicate that such architectures can enable over 300,000 times energy efficiencies over traditional high performance computing architectures when processing large neural networks.

Energy efficient perceptron pattern recognition using segmented memristor crossbar arrays

This paper presents a segmented memristor crossbar array capable of performing pattern recognition tasks. Partial transistor isolation is used to segment smaller memristor crossbar structures. The synaptic density is less than that of a single large memristor crossbar, although this system is much more energy efficient. This system also reduces the amount of unwanted current paths that are a byproduct of large restive crossbar arrays. The proposed system is validated using SPICE simulations that utilize an accurate memristor model that we previously published. Additionally, wire resistance between memristor devices is accounted for to study how a realistic memristor circuit would perform in terms of energy, area, and ability to classify patterns. In this detailed implementation, the proposed system was shown to classify both 16 and 32 pixel images.

Memristor SPICE Modeling

Modeling of memristor devices is essential for memristor based circuit and system design. This chapter presents a review of existing memristor modeling techniques and provides simulations that compare several existing models to published memristor characterization data. A discussion of existing models is presented that explains how the equations of each relate to physical device behaviors.

Analysis of a memristor based 1T1M crossbar architecture

The recently discovered memristor has the potential to be the building block of a high-density memory system. A memristor based crossbar memory system was analyzed in terms of timing and switching energy using SPICE. The memristor model in the simulations was designed to match the I–V characteristics of three different published devices. The simulation results for each device were compared to demonstrate the performance of a one transistor one memristor (1T1M) memristor crossbar.

Hybrid crossbar architecture for a memristor based cache

This paper describes a new memristor crossbar architecture that is proposed for use in a high density cache design. This design has less than 10% of the write energy consumption than a simple memristor crossbar. Also, it has up to 3 times the bit density of an STT-MRAM system and up to 11 times the bit density of an SRAM architecture. The proposed architecture is analyzed using a detailed SPICE analysis that accounts for the resistance of the wires in the memristor structure. Additionally, the memristor model used in this work has been matched to specific device characterization data to provide accurate results in terms of energy, area, and timing. The proposed memory system was analyzed by modeling two different devices that vary in resistance range and switching time. This system does not require that the memristor devices have inherent diode effects which limit alternate current paths. Therefore this system is capable of utilizing a much broader class of devices.An architectural analysis has also been completed that shows how the memory system may perform as a cache memory. A hybrid cache structure was used to alleviate the long write latencies of memristor devices. This approach consisted of the tag array being made of SRAM cells while the data array was made of the memristor circuit proposed. This hybrid scheme allows multiple reads and writes to concurrently access different sub-arrays within a cache. The performance of these novel memristor based caches was compared to SRAM and STT-MRAM based caches through detailed simulations. The results show that the memristor caches are denser and allow better performance along with lower system power when compared to the STT-MRAM and SRAM caches.

Memristor crossbar deep network implementation based on a Convolutional neural network

This paper presents a simulated memristor crossbar implementation of a deep Convolutional Neural Network (CNN). In the past few years deep neural networks implemented on GPU clusters have become the state of the art in image classification. They provide excellent classification ability at the cost of a more complex data manipulation process. However once these systems are trained, we show that the analog crossbar circuits in this paper can highly parallelize the recognition phase of a CNN algorithm. One of the drawbacks of using memristors to carry out computations is that the data stored will likely have less precision when compared to typical 32-bit floating point memory. However, we show the proposed system is capable of operating with zero loss in classification accuracy if the memristors utilized are able to store at least 16 unique values (essentially acting as 4-bit devices). To the best of our knowledge, this is the first paper that presents a memristor based circuit for implementing CNN recognition. This is also the first paper that provides a circuit for precise memristor based analog convolution.