Rashmi Jha

A capacitance-based methodology for work function extraction of metals on high-/spl kappa/

This letter presents a methodology to accurately extract the work function of metal electrodes on high-/spl kappa/ dielectrics with various charge distributions. A mathematical analysis including sources of errors was used to study the effect of charge distribution in gate dielectric stacks on the flatband voltage of the device. The calculations are verified by experimental results obtained for Ru-Ta alloys on HfO/sub 2/ and SiO/sub 2/ gate dielectric stacks. It is shown that accounting for the appropriate charge model is imperative for accurate calculation of workfunction on high-/spl kappa//SiO/sub 2/ gate dielectric stacks.

A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process

For the first time, we have demonstrated a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2. Record NMOS/PMOS drive currents of 1000/575 muA/mum, respectively, have been achieved at 1 nA/mum off-current and 1.1 V Vdd with a low cost process. With this high performance transistor, Vdd can be further scaled to 1.0 V for active power reduction. Through aggressive EOT scaling and band-edge work-function metal gate stacks, appropriate Vts and superior short channel control has been achieved for both NMOS and PMOS at Lgate = 30 nm. Compared to SiON-Poly, 30% RO delay reduction has been demonstrated with HK-MG devices. 40% Vt mismatch reduction has been shown with the Tinv scaling. Furthermore, it has been shown that the 1/f noise and transistor reliability exceed the technology requirements.

Novel synaptic memory device for neuromorphic computing

This report discusses the electrical characteristics of two-terminal synaptic memory devices capable of demonstrating an analog change in conductance in response to the varying amplitude and pulse-width of the applied signal. The devices are based on Mn doped HfO2 material. The mechanism behind reconfiguration was studied and a unified model is presented to explain the underlying device physics. The model was then utilized to show the application of these devices in speech recognition. A comparison between a 20 nm × 20 nm sized synaptic memory device with that of a state-of-the-art VLSI SRAM synapse showed ~10× reduction in area and >106 times reduction in the power consumption per learning cycle.

Compatibility of dual metal gate electrodes with high-k dielectrics for CMOS

Dual metal electrodes such as Ru, Ru-Ta alloy, TaN and TaSiN were investigated on low EOT single layer HfO/sub 2/ and stacked HfO/sub 2//SiO/sub 2/ gate dielectrics. It was found that the work function values of metal gates on HfO/sub 2/ and on SiO/sub 2/ are similar. Thermal anneal studies of selected metals on the above dielectrics were also performed to evaluate the change in EOT and V/sub FB/ values.

Work Function Tuning Via Interface Dipole by Ultrathin Reaction Layers Using AlTa and AlTaN Alloys

This letter presents a route for tuning the metal gate effective work function via interface dipoles formed using AlTa and AlTaN alloys. It was found that the AlTa alloy has a higher effective work function (4.45 eV) compared to either Al (~ 4.1 eV) or Ta (4.2 eV) gates on SiO 2 at 400 degC. This increase in effective work function was attributed to interface dipoles formed at the gate electrode and dielectric interface. The origin of this dipole is attributed to a reaction between the AlTa alloy and the dielectric layer. Similar AlTa effective work function tuning was also observed on high-k dielectrics. However, since the AlTa alloy is not thermally stable on SiO2, nitrogen was added to stabilize the electrode. The addition of N stabilizes the equivalent oxide thickness while still allowing for work function tuning under high temperatures. AlTaN alloys were deposited by reactive sputtering and resulted in an effective work function of ~ 5.1 eV after a 1000 degC anneal, making them suitable for PMOS gate applications

Switching Characteristics of

We report the switching characteristics of RRAM devices consisting of Ru/HfO2/TiO2-x/Ru stacks with and without an external access device. In addition to bistable switching, we also achieved an analog reconfiguration of resistance by controlling the compliance current or the reset voltage to achieve a low-resistance state (LRS) or a high-resistance state (HRS), respectively. All intermediate states were nonvolatile in nature. The transport studies using temperature-dependent I-V measurement indicated the mechanism of conduction to be ionic in LRS and Frenkel-Poole in both HRS and virgin resistance state of a device.

\hbox{Ru/HfO}_{2} \hbox{/TiO}_{2-x}\hbox{/Ru}

We report the switching dynamics and charge transport studies on Ru/HfO2/TiOx/Ru resistive random access memory devices in low resistance state (LRS), high resistance state (HRS), and virgin resistance state (VRS). The charge transport in LRS is governed by Ohmic conduction of electrons through local filamentary paths while it is governed by a combination of Frenkel-Poole emission and trap assisted tunneling process in HRS and VRS. The area of the filament in LRS is extracted and related to the compliance current. The thickness of the re-oxidized filament is extracted and related to the reset voltage in HRS. The energy consumed during the reset process was analyzed on the time-scale to experimentally demonstrate joule-heating mediated oxidation dynamics of filament during device reset.

RRAM Devices for Digital and Analog Nonvolatile Memory Applications

CMOS devices with high-k/metal gate stacks have been fabricated using a gate-first process flow and conventional stressors at gate lengths of 25 nm, highlighting the scalability of this approach for high performance SOI CMOS technology. AC drive currents of 1630muA/mum and 1190muA/mum have been demonstrated in 45 nm ground-rules at 1V and 200nA/mum off current for nFETs and pFETs, at a Tinv of 14 and 15 respectively. The drive currents were achieved using a simplified high-k/metal gate integration scheme with embedded SiGe and dual stress liners (DSL) and without utilizing additional stress enhancers. Devices have been fabricated with Tinvs down to 12 and 10.5 demonstrating the scalability of this approach for 32 nm and beyond.

Switching dynamics and charge transport studies of resistive random access memory devices

The effective work function of PMOS metal gate electrode as a function of intentionally altered HfO2 surfaces was investigated. The impact of capping layers, diffusion barriers and interfacial layers on the final work function was also examined. The factors responsible for the change in the effective work function after subsequent thermal treatments were identified and routes to maintain the high effective work function have been demonstrated

Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate

The workfunction behavior and stability of several candidate metal gate electrodes on HfO/sub 2/ was carefully examined and correlated with processing parameters such as anneal temperatures and oxygen exposures. Transition metals and their nitrides, binary metal alloys and refractory metals were studied on MOCVD HfO/sub 2/ dielectrics of varying thicknesses. Binary low work function Mo-Ta alloys were also investigated on HfO/sub 2/.