Ratul Kumar Baruah

A Dual-Material Gate Junctionless Transistor With High-

In this paper, we present a simulation study of analog circuit performance parameters for a symmetric double-gate junctionless transistor (DGJLT) using dual-material gate along with high- k spacer dielectric (DMG-SP) on both sides of the gate oxides of the device. The characteristics are demonstrated and compared with DMG DGJLT and single-material (conventional) gate (SMG) DGJLT. The DMG DGJLT presents superior transconductance (Gm), early voltage (VEA), and intrinsic gain (GmRO) compared with SMG DGJLT. The values are further improved for DMG-SP DGJLT, because high- k spacer enhances the fringing electric fields through the spacer.

k

In this paper, the impact of process induced variations on the electrical characteristics of a junctionless symmetric double-gate transistor (DGJLT) is reported for the first time. The process parameters considered here are gate length (L), thickness of silicon film (Tsi) and gate oxide thickness (Tox). The impact of these process parameters on the electrical parameters viz., ON current, threshold voltage (VT) and subthreshold slope (SS) are systematically investigated with the help of extensive device simulations and compared with conventional symmetric doublegate transistor (DGMOS). It is seen that ON current variation with silicon thickness is higher for DGJLT compared to DGMOS. Threshold voltage of DGJLT is more sensitive to silicon thickness and gate oxide thickness as compared to DGMOS. The overall SS variation is negligible in DGJLT compared to DGMOS.

Spacer for Enhanced Analog Performance

In this paper, the performance of a short channel symmetric double-gate junctionless transistor (DGJLT) is reported at lower drain voltage aiming low power digital applications. The performance parameters namely drain current (ID), threshold voltage (VT), subthreshold slope (SS), drain induced barrier lowering (DIBL), and ON-state to OFFstate current ratio (ION/IOFF) for an n-channel DGJLT are systematically investigated with the help of extensive device simulations. The device characteristics are compared with inversion mode counterpart i.e., double-gate metal-oxide-semiconductor (DGMOS) of similar dimension. DGJLT is found to have significantly overall better performance compared to inversion mode DGMOS transistor at lower drain voltage.

Estimation of process-induced variations in double-gate junctionless transistor

In this paper, analog performance of bulk planer junctionless transistor (BPJLT) is reported for the first time. The analog performance parameters, namely transconductance/drain current ratio (Gm/ID), intrinsic gain (GmRO) and unity gain frequency (fT) for n-type BPJLT are systematically investigated with the help of extensive device simulations. The results are then compared with silicon on insulator junctionless transistor (SOI JLT). BPJLT is found to have significantly overall better performance as compared to SOI JLT in regard of analog behaviour.

Double-gate junctionless transistor for low power digital applications

In this paper, we present a simulation study of analog circuit performance parameters of a dual material double-layer gate stack (high-k/SiO2) (DM-DGS) symmetric double-gate junctionless transistor (DGJLT). The characteristics are demonstrated and compared with dual material gate (DMG) DGJLT and single material (conventional) gate (SMG) DGJLT. DMG DGJLT present superior transconductance (Gm), early voltage (VEA) and intrinsic gain (GmRO) compared to SMG DGJLT. These parameters are further improved for DM-DGS DGJLT and it can be attributed to their better gate control on the channel region.