Roy Paily

A Dual-Material Gate Junctionless Transistor With High-

In this paper, we present a simulation study of analog circuit performance parameters for a symmetric double-gate junctionless transistor (DGJLT) using dual-material gate along with high- k spacer dielectric (DMG-SP) on both sides of the gate oxides of the device. The characteristics are demonstrated and compared with DMG DGJLT and single-material (conventional) gate (SMG) DGJLT. The DMG DGJLT presents superior transconductance (Gm), early voltage (VEA), and intrinsic gain (GmRO) compared with SMG DGJLT. The values are further improved for DMG-SP DGJLT, because high- k spacer enhances the fringing electric fields through the spacer.

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In high speed flash ADCs, the thermometer coded output of the comparators is converted to binary code by a thermometer-to-binary decoder using a ROM. The ROM is simple and straightforward to design but it requires bubble error correction/suppression circuitry. A novel ROM architecture suitable for high speed operation with bubble error suppression is described in this paper. An 800 MHz 6-bit flash ADC is designed and simulated to verify the performance of different ROM architectures. The proposed ROM architecture eliminates the need of gray encoded ROM as well as gray to binary conversion circuitry, hence reduces the complexity and enhances the performance.

Spacer for Enhanced Analog Performance

The presence of weak spots and pinholes in ultrathin gate oxides significantly increases the leakage current, thereby degrading the device performance. This paper proposes a method, which identifies the weak spots in thermally grown gate oxide and repairs them by selective anodization. By controlling the applied voltage, it is ensured that current flows only through the weak spots in the oxide during anodization. Anodic oxide therefore grows over these weak spots, improving the reliability of the oxide without increasing the gate oxide thickness. Significant improvement in electrical characteristics was observed in the gate oxides treated by anodic oxidation.

An improved ROM architecture for bubble error suppression in high speed flash ADCs

This work focuses on the VLSI design aspect of high- speed maximum a posteriori (MAP) probability decoders which are intrinsic building-blocks of parallel turbo decoders. For the logarithmic-Bahl-Cocke-Jelinek-Raviv (LBCJR) algorithm used in MAP decoders, we have presented an ungrouped backward recursion technique for the computation of backward state metrics. Unlike the conventional decoder architectures, MAP decoder based on this technique can be extensively pipelined and retimed to achieve higher clock frequency. Additionally, the state metric normalization technique employed in the design of an add-compare-select-unit (ACSU) has reduced critical path delay of our decoder architecture. We have designed and implemented turbo decoders with 8 and 64 parallel MAP decoders in 90 nm CMOS technology. VLSI implementation of an 8 × parallel turbo-decoder has achieved a maximum throughput of 439 Mbps with 0.11 nJ/bit/iteration energy-efficiency. Similarly, 64 × parallel turbo-decoder has achieved a maximum throughput of 3.3 Gbps with an energy-efficiency of 0.079 nJ/bit/iteration. These high-throughput decoders meet peak data-rates of 3GPP-LTE and LTE-Advanced standards.

Improvement in electrical characteristics of ultrathin thermally grown SiO 2 by selective anodic oxidation

Present day applications require various kinds of images and pictures as sources of information for interpretation and analysis. Whenever an image is converted from one form to another, such as digitizing, scanning, transmitting, storing, etc., some form of degradation occurs at the output. Hence, the output image has to undergo a process called image enhancement which consists of a collection of techniques that seek to improve the visual appearance of an image. This work addresses the implementation of image enhancement algorithms like brightness control, contrast adjustment and histogram equalization on FPGA that have become a competitive alternative for high-performance digital signal processing applications.

High-Throughput Turbo Decoder With Parallel Architecture for LTE Wireless Communication Standards

RFID is evolving as a major technology enabler for identifying and tracking goods. RFID applications in biomedical area not only need to detect but also require monitoring and transmitting vital signals like the electrocardiogram (and heartbeat), blood pressure, body temperature, etc. The basic building blocks of an RFID tag for biomedical application are studied. The sizing and powering up of the tags are critical issues and this paper mainly focuses on the design and optimization of the inductor for an RFID circuit. UHF is chosen for this application mainly because of the practical values of inductance that can be realized in CMOS chip to operate at this operating frequency. The layout parameters of inductor are optimized for a maximum Q-factor value at the desired frequency. Using the optimized inductor, the functioning of the important blocks of an RFID tag such as power feeding circuit, heartbeat detection circuit as well as the modulation circuit is verified. This work would be very relevant for the remote monitoring of biomedical signals.

FPGA implementation of image enhancement algorithms

This paper presents architecture of block-level-parallel layered decoder for irregular LDPC code. It can be reconfigured to support various block lengths and code rates of IEEE 802.11n (WiFi) wireless-communication standard. We have proposed efficient comparison techniques for both column and row layered schedule and rejection-based high-speed circuits to compute the two minimum values from multiple inputs required for row layered processing of hardware-friendly min-sum decoding algorithm. The results show good speed with lower area as compared to state-of-the-art circuits. Additionally, this work proposes dynamic multi-frame processing schedule which efficiently utilizes the layered-LDPC decoding with minimum pipeline stages. The suggested LDPC-decoder architecture has been synthesized and post-layout simulated in 90 nm-CMOS process. This decoder occupies 5.19 mm2 area and supports multiple code rates like 1/2, 2/3, 3/4 & 5/6 as well as block-lengths of 648, 1296 & 1944. At a clock frequency of 336 MHz, the proposed LDPC-decoder has achieved better throughput of 5.13 Gbps and energy efficiency of 0.01 nJ/bits/iterations, as compared to the similar state-of-the-art works.

RFID Circuit Design with Optimized CMOS Inductor for Monitoring Biomedical Signals

Square microhotplates find their usefulness because of ease of fabrication and high yield compared with bridge or spider membrane. It has been already established that often in microhotplates, an insulation layer is required to separate the thermal domain from other application domains such as gas sensor. However, enhancing the performance of microhotplate by the optimization of insulation layer area, especially in terms of power and uniformity aspects, has not been explored yet. Nevertheless, the improvement in the uniformity was also accompanied by increased power consumption. An analytical model is developed for the optimization of the insulation nitride area. The model is compared with the finite element method simulations and the results are in close agreement with errors within 5%. Because of the modular nature of the developed model, the thermal losses in the insulation layer could be estimated separately. Since power consumption of the microhotplate depends on the thermal mass, an optimized dimensions of heat spreader can bring multiple advantages such as better uniformity, higher temperature, and minimized power overhead. Compared with insulation nitride dimensions of 250 × 250 × 8 μm, for attaining a temperature of 550 K, an optimized insulation nitride dimension of 120 × 120 × 8 μm has improved the thermal uniformity by 40.1%, power consumption by 34.48%, and maximum operating temperature by 28.45% when 2 V input voltage is applied.

High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule

A MEMS based energy harvesting device is designed to convert mechanical vibration energy to electrical energy via piezoelectric effect. In order to improve the performances of the device, the geometry has been optimized by using moving mesh ALE model available in Comsol Multiphysics. The thickness, length and width of metal and ZnO are varied to get maximum displacement and voltage. The length, width and thickness of cantilever are obtained as 2000µm × 120µm × 5.4µm. In order to lower resonance frequency and maximize the output voltage, a proof mass is placed on tip of cantilever. The dimensions of proof mass are 237µm × 120µm × 237µm and mass is 0.145mg. Cantilever beam resonated at a frequency of 630Hz with acceleration of 1g and an output voltage obtained for d31 is 1.06V and for d33 is 3.85V . The proposed device is suitable for vibration energy harvesting and can be used as potential micro-generator.

Analytical Modeling of Square Microhotplate for Gas Sensing Application

In this paper, we have considered different circuit techniques to reduce leakage currents in digital CMOS circuits. In this study, an emphasis is given on gate leakage and sub threshold components of leakage currents. The leakage currents of 65 nm and 45 nm technology node NMOS/PMOS transistor and simple CMOS inverter are compared with low leakage current circuits. The modified stack forcing scheme with optimum iso input load condition gave leakage reduction by a factor of 7 compared to the normal stack forcing technique.