Raul Blazquez

Microwatt embedded processor platform for medical system-on-chip applications

A medical system-on-chip (SoC) that integrates an ARM Cortex-M3 processor is presented. Ultra-low power operation is achieved via 0.5–1.0 V operation, a 28 fW/bit fully differential subthreshold 6T SRAM, a 90%-efficient DC-DC converter, and a 100-nJ fast Fourier transform (FFT) accelerator to reduce processor workload. Using a combination of novel circuit design, system architecture, and SoC implementation, the first sub-microwatt per channel electroencephalograph (EEG) seizure detection is demonstrated.

System design considerations for ultra-wideband communication

This article discusses issues associated with high-data-rate pulsed ultra-wideband system design, including the baseband processing, transmitter, antenna, receiver, and analog-to-digital conversion. A modular platform is presented that can be used for developing system specifications and prototyping designs. This prototype modulates data with binary phase shift keyed pulses, communicates over a wireless link using UWB antennas and a wideband direct conversion front-end, and samples the received signal for demodulation. Design considerations are introduced for a custom chipset that operates in the 3.1-10.6 GHz band. The chipset is being designed using the results from the discrete prototype.

Low-Power Impulse UWB Architectures and Circuits

Ultra-wide-band (UWB) communication has a variety of applications ranging from wireless USB to radio frequency (RF) identification tags. For many of these applications, energy is critical due to the fact that the radios are situated on battery-operated or even batteryless devices. Two custom low-power impulse UWB systems are presented in this paper that address high- and low-data-rate applications. Both systems utilize energy-efficient architectures and circuits. The high-rate system leverages parallelism to enable the use of energy-efficient architectures and aggressive voltage scaling down to 0.4 V while maintaining a rate of 100 Mb/s. The low-rate system has an all digital transmitter architecture, 0.65 and 0.5 V radio-frequency (RF) and analog circuits in the receiver, and no RF local oscillators, allowing the chipset to power on in 2 ns for highly duty-cycled operation.

A baseband processor for impulse ultra-wideband communications

This paper presents a baseband processor architecture for pulsed ultra-wideband signals. It consists of an analog-to-digital converter (ADC), a clock generation system, and a digital back-end. The clock generation system provides different phases of a 300-MHz clock using four differential inverter stages. The specification of the jitter standard deviation is 100 ps. The Flash interleaved ADC provides four bit samples at 1.2 Gsps. The back-end uses parallelization to process these samples and to reduce the signal acquisition time to 65 /spl mu/s. The entire synchronization algorithm is implemented in the digital domain, without feeding any signals back to the clock control. The baseband processor and ADC were implemented on the same 0.18-/spl mu/m CMOS die at 1.8 V as part of a complete baseband transceiver. A wireless data rate of 193 kb/s is demonstrated.

Coarse acquisition for ultra wideband digital receivers

Ultra wideband (UWB) radio is a new wireless technology that uses sub-nanosecond pulses to transmit information, resulting in a bandwidth greater than 1 GHz. The problem of synchronizing a receiver with the incoming signal grows in complexity as the signal bandwidth increases. This paper addresses coarse synchronization in UWB receivers. It analyzes how the design of the correlation process affects the time to achieve synchronization, highlighting the importance of the probability of false alarm in its performance.

Microwatt Embedded Processor Platform for Medical System-on-Chip Applications

Battery life specifications drive the power consumption requirements of integrated circuits in implantable, wearable, and portable medical devices. In this paper, we present an embedded processor platform chip using an ARM Cortex-M3 suitable for mapping medical applications requiring microwatt power consumption. Ultra-low-power operation is achieved via 0.5-1.0 V operation, a 28 fW/bit fully differential subthreshold 6T SRAM, a 90%-efficient DC-DC converter, and a 100-nJ fast Fourier transform (FFT) accelerator to reduce processor workload. Using a combination of novel circuit design, system architecture, and SoC implementation, the first sub-microwatt per channel electroencephalograph (EEG) seizure detection is demonstrated.

A baseband processor for pulsed ultra-wideband signals

This paper presents a baseband processor for pulsed ultrawideband signals. It consists of an analog to digital converter (ADC), a clock generation system and a digital back-end. The FLASH interleaved ADC provides four bit samples at 1.2 GSPS. The back-end uses parallelization to process these samples and to reduce the signal acquisition time to 70 /spl mu/s. The baseband processor was implemented in the same 0.18 /spl mu/m CMOS chip as a part of a complete transceiver. A complete 193 kbps wireless link is demonstrated.

Digital architecture for an ultra-wideband radio receiver

The paper presents analysis of a digital ultra-wideband (UWB) radio receiver operating in the 3.1 GHz to 10.6 GHz band. Analog-to-digital converter (ADC) bit precision is analyzed on two types of UWB signals - OFDM UWB and pulsed UWB - all in the presence of additive white Gaussian noise (AWGN) and a narrowband interferer in the channel. The paper shows how probability of error and the bit resolution of the ADC can be scaled depending on the signal-to-noise ratio (SNR), signal-to-interference ratio (SIR), and the type of UWB signal. It also includes considerations on timing recovery for pulsed UWB.

An Energy Efficient Sub-Threshold Baseband Processor Architecture for Pulsed Ultra-Wideband Communications

This paper describes how parallelism in the digital baseband processor can reduce the energy required to receive ultra-wideband (UWB) packets. The supply voltage of the digital baseband is lowered so that the correlator operates near its minimum energy point resulting in a 68% energy reduction across the entire baseband. This optimum supply voltage occurs below the threshold voltage, placing the circuit in the sub-threshold region. The correlator and the rest of the baseband must be parallelized to maintain throughput at this reduced voltage. While sub-threshold operation is traditionally used for low energy, low frequency applications such as wrist-watches, this paper examines how sub-threshold operation can be applied to low energy, high performance applications. The correlators are further parallelized for a 31x reduction in the synchronization time, which along with duty-cycling, lowers the energy per packet by 43% for a 500 byte packet. Simulation results for a 100 Mbps UWB baseband processor are described

Direct Conversion Pulsed UWB Transceiver Architecture

Ultra-wideband (UWB) communication is an emerging wireless technology that promises high data rates over short distances and precise locationing. The large available bandwidth and the constraint of a maximum power spectral density drives a unique set of system challenges. This paper addresses these challenges using two UWB transceivers and a discrete prototype platform.