Brian P. Ginsburg

An energy-efficient charge recycling approach for a SAR converter with capacitive DAC

A new method for switching the capacitors in the DAC capacitor array of a successive approximation register (SAR) ADC is presented. By splitting the MSB capacitor into b - 1 binary scaled sub-capacitors, the average switching energy of the array can be reduced by 37% compared to a conventional switching method. A formal solution of the switching energy in four different switching methods is included, and the equations are verified using HSPICE simulations of a 10b capacitor array in a 0.18 /spl mu/m CMOS process.

500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC

A 500-MS/s 5-bit ADC for UWB applications has been fabricated in a 65-nm CMOS technology using no analog-specific processing options. The time-interleaved successive approximation register (SAR) architecture has been chosen due to its simplicity versus flash and its amenability to scaled technologies versus pipelined, which relies on operational amplifiers. Six time-interleaved channels are used, sharing a single clock operating at the composite sampling rate. Each channel has a split capacitor array that reduces switching energy, increases speed, and has similar INL and decreased DNL, as compared to a conventional binary-weighted array. A variable delay line adjusts the instant of latch strobing to reduce preamplifier currents. The ADC achieves Nyquist performance, with an SNDR of 27.8 and 26.1 dB for 3.3and 239 MHz inputs, respectively. The total active area is 0.9mm2, and the ADC consumes 6 mW from a 1.2-V supply

Dual Time-Interleaved Successive Approximation Register ADCs for an Ultra-Wideband Receiver

Ultra-wideband radio requires Nyquist sampling rates of at least 500 MS/s with low resolutions. While flash is the traditional choice for these specifications, a comparative energy model is used to show the potential energy savings of the time-interleaved successive approximation register architecture, which requires only a linear number of comparisons versus exponential for flash. A dual 500-MS/s, 5-bit ADC chip is implemented in a 0.18-mum CMOS process, with both ADCs synchronized for use in an I/Q UWB receiver. Each ADC uses a 6-way time-interleaved SAR topology with full custom logic, self-timed bit-cycling, and duty cycling of the comparator preamplifiers to enable 500-MS/s operation with 7.8 mW power consumption. The output resolution is adjustable down to the 1-bit level for additional power savings

System design considerations for ultra-wideband communication

This article discusses issues associated with high-data-rate pulsed ultra-wideband system design, including the baseband processing, transmitter, antenna, receiver, and analog-to-digital conversion. A modular platform is presented that can be used for developing system specifications and prototyping designs. This prototype modulates data with binary phase shift keyed pulses, communicates over a wireless link using UWB antennas and a wideband direct conversion front-end, and samples the received signal for demodulation. Design considerations are introduced for a custom chipset that operates in the 3.1-10.6 GHz band. The chipset is being designed using the results from the discrete prototype.

Low-Power Impulse UWB Architectures and Circuits

Ultra-wide-band (UWB) communication has a variety of applications ranging from wireless USB to radio frequency (RF) identification tags. For many of these applications, energy is critical due to the fact that the radios are situated on battery-operated or even batteryless devices. Two custom low-power impulse UWB systems are presented in this paper that address high- and low-data-rate applications. Both systems utilize energy-efficient architectures and circuits. The high-rate system leverages parallelism to enable the use of energy-efficient architectures and aggressive voltage scaling down to 0.4 V while maintaining a rate of 100 Mb/s. The low-rate system has an all digital transmitter architecture, 0.65 and 0.5 V radio-frequency (RF) and analog circuits in the receiver, and no RF local oscillators, allowing the chipset to power on in 2 ns for highly duty-cycled operation.

Highly Interleaved 5-bit, 250-MSample/s, 1.2-mW ADC With Redundant Channels in 65-nm CMOS

This successive approximation register ADC uses time-interleaving to gain the energy advantage of slower circuits (reduced supply voltage and improved bias points) without sacrificing high speed operation. The drawbacks of interleaving are addressed through architectural solutions. Channel redundancy counteracts the severe yield loss that parallel circuits experience due to local variation. Clock partitioning restricts the distribution of the precise, high-speed sampling clock to three centrally located sampling networks. Only a low frequency clock is distributed across the majority of die area. The skew-resistant global top-plate sampling network is extended to allow overlapped sampling windows without introducing extra sources of crosstalk. The 36 -way interleaved 5-bit ADC operates with a core voltage of 800 mV and consumes 1.20 mW total power at 250 MS/s. At Nyquist, the SNDR is 28.4 dB. The 6 redundant channels (17% overhead) increase the yield of the 24 measured chips from 42% to 88%.

Highly Interleaved 5b 250MS/s ADC with Redundant Channels in 65nm CMOS

The 250 MS/S ADC has 36 time-interleaved 5b SAR ADC channels operating at 800 mV. Parallelism is used specifically to improve energy efficiency, and architectural solutions address the limitations of interleaving. Redundancy is used as an efficient technique to counteract the yield loss from local variation. A hierarchical top- plate sampling network reduces timing skew with extended sampling times and permits a partitioned clock network for minimum distribution requirements.

Dual scalable 500MS/s, 5b time-interleaved SAR ADCs for UWB applications

A dual 500MS/s, 5b ADC chip is implemented in a 0.18 mum CMOS process. The two ADCs have synchronized sampling for use in an I/Q UWB receiver. Each ADC has a 6-way time-interleaved successive approximation register topology and uses full custom logic, self-timed bit-cycling, and duty cycling of the comparator preamplifiers to enable 500MS/s operation with 7.8mW power consumption

A 160 GHz Pulsed Radar Transceiver in 65 nm CMOS

This paper presents a 160 GHz center frequency pulsed 65 nm CMOS transceiver for short range radar applications. Four phased array transceivers were implemented in a single chip with antennas implemented in a BGA package. The implemented transmitter is capable of producing pulses of 100 ps widths ( >20 GHz RF bandwidth) at a 160 GHz carrier frequency. The measured effective isotropic radiated power (EIRP) is 18.8 dBm for continuous wave outputs. The analog beam forming receiver achieves an overall gain of 42.5 dB, -14 dBm IP1dB, 7 GHz bandwidth, and a noise figure of 22.5 dB. The sliding window time-dilation baseband relaxes the output data rate and subsequent digital processing requirements. Fine grained duty cycling reduces power dissipation. The entire chip consumes 2.2 W from 1.2/1.4 V supplies in a 65 nm digital CMOS process.

Direct Conversion Pulsed UWB Transceiver Architecture

Ultra-wideband (UWB) communication is an emerging wireless technology that promises high data rates over short distances and precise locationing. The large available bandwidth and the constraint of a maximum power spectral density drives a unique set of system challenges. This paper addresses these challenges using two UWB transceivers and a discrete prototype platform.