Raul Finker

A real-time driver identification system based on artificial neural networks and cepstral analysis

The availability of advanced driver assistance systems (ADAS), for safety and well-being, is becoming increasingly important for avoiding traffic accidents caused by fatigue, stress, or distractions. For this reason, automatic identification of a driver from among a group of various drivers (i.e. real-time driver identification) is a key factor in the development of ADAS, mainly when the drivers comfort and security is also to be taken into account. The main focus of this work is the development of embedded electronic systems for in-vehicle deployment of driver identification models. We developed a hybrid model based on artificial neural networks (ANN), and cepstral feature extraction techniques, able to recognize the driving style of different drivers. Results obtained show that the system is able to perform real-time driver identification using non-intrusive driving behavior signals such as brake pedal signals and gas pedal signals. The identification of a driver from within groups with a reduced number of drivers yields promising identification rates (e.g. 3-driver group yield 84.6%). However, real-time development of ADAS requires very fast electronic systems. To this end, an FPGA-based hardware coprocessor for acceleration of the neural classifier has been developed. The coprocessor core is able to compute the whole ANN in less than 4 μs.

An intelligent embedded system for real-time adaptive extreme learning machine

Extreme learning machine (ELM) is an emerging approach that has attracted the attention of the research community because it outperforms conventional back-propagation feed-forward neural networks and support vector machines (SVM) in some aspects. ELM provides a robust learning algorithm, free of local minima, suitable for high speed computation, and less dependant on human intervention than the above methods. ELM is appropriate for the implementation of intelligent embedded systems with real-time learning capability. Moreover, a number of cutting-edge applications demanding a high performance solution could benefit from this approach. In this work, a scalable hardware/software architecture for ELM is presented, and the details of its implementation on a field programmable gate array (FPGA) are analyzed. The proposed solution provides high speed, small size, low power consumption, autonomy, and true capability for real-time adaptation (i.e. the learning stage is performed on-chip). The developed system is able to deal with highly demanding multiclass classification problems. Two real-world applications are presented, a benchmark problem of the Landsat images database, and a novel driver identification system for smart car applications. Experimental results that validate the proposal are provided.

Dynamic Partial Reconfiguration in Embedded Systems for Intelligent Environments

In this paper we propose to apply the Dynamic Partial Reconfiguration (DPR) technology to embedded systems intended for Intelligent Environments. To reach this goal, we have developed a system based on a Field Programmable Gate Array (FPGA) in which high performance hardware modules can be reconfigured on-line according to the necessities of the system at each moment. Two different implementations have been carried out to measure the time required to reconfigure each module and also to measure the FPGA resources that can be saved if we keep configured only the modules that are required at each time. The Obtained results show how this technique offers advantages in cost, size and power when applied to embedded systems for intelligent environments.

Scalable parallel architecture for singular value decomposition of large matrices

Singular Value Decomposition (SVD) is a key linear algebraic operation in many scientific and engineering applications, many of them involving high dimensionality datasets and real-time response. In this paper we describe a scalable parallel processing architecture for accelerating the SVD of large m × n matrices. Based on a linear array of simple processing-units (PUs), the proposed architecture follows a double data-flow paradigm (FIFO memories and a shared-bus) for optimizing the time spent in data transferences. The PUs, which perform elemental column-pair evaluations and rotations, have been designed for an efficient utilization of available FPGA resources and to achieve maximum algorithm speed-ups. The architecture is fully scalable from a two-PU scheme to an arrangement with as many as n/2 PUs. This allows for a trade-off between occupied area and processing acceleration in the final implementation, and permits the SVD processor to be implemented both on low-cost and high-end FPGAs. The system has been prototyped on Spartan-6 and Kintex-7 devices for performance comparison.

Multilevel adaptive neural network architecture for implementing single-chip intelligent agents on FPGAs

The powerful synergy of neural networks and reconfigurable hardware provides a solid foundation for the development of high performance embedded systems able to efficiently adapt to changing requirements. Adaptation at different levels - ranging from the physical level to the system level-can be combined to develop efficient solutions by means of FPGA technology. In this work, a multilevel adaptation scheme for the development of intelligent agents is proposed. Software learning algorithms are applied to adapt the agent behavior (i.e. neural network parameters) at the system level, while dynamic partial reconfiguration (DPR) is used to modify the agent at the physical and architectural level (i.e. neural network topology). Firstly, a multilevel adaptive intelligent agent is able to manage its resources efficiently in order to meet time-varying demands such as speed performance and power consumption. Secondly, from the behavioral viewpoint, multilevel adaptation provides the intelligent agent with high plasticity and flexibility. An FPGA-based intelligent agent has been successfully deployed for a real-time control problem in an inhabited intelligent environment. Results obtained show that the agent is able to adapt itself to changes in the environment in a lifelong mode.

ELM-based hyperspectral imagery processor for onboard real-time classification

Hyperspectral imagery is being widely used for accurate object detection and terrain feature classification. Modern imaging spectrometers produce huge amounts of data that are compressed onboard and downloaded to ground stations to be processed. Increasing spectral resolution and data acquisition rates demand more efficient compression techniques to meet downlink bandwidth restrictions. A different approach to reducing data-transfer bottlenecks consists of processing hyperspectral imagery information onboard. Real-time onboard processing would, at the same time, broaden the scope of missions that spacecrafts and aircrafts carrying hyperspectral cameras could fulfill by providing them with immediate decision-making capacity in critical circumstances. This paper investigates the use of Extreme Learning Machines (ELMs) for the classification of high dimensional data, and how specialized hardware and application-specific processor design can help to produce high performance, lightweight, and reduced power consumption systems for onboard hyperspectral imagery processing.

Controlled-Accuracy Approximation of Nonlinear Functions for Soft Computing Applications: A High Performance Co-proccessor for Intelligent Embedded Systems

Intelligent embedded systems can be found everywhere in a variety of innovative applications. The main challenge consists in developing small-size single-chip embedded systems with low power consumption, capable of processing data and intelligent algorithms with the required speed. These key issues are normally carefully analyzed during the design process of embedded systems with the aim of meeting the required specifications. However, the problem of accuracy is hardly ever explored at early stages of the design flow, even though too low accuracy could limit digital hardware performance in a crucial way. This piece of work proposes a controlled accuracy approximation scheme of nonlinear functions based on Taylors Theorem and the Lagrange form of the remainder. A hardware co-processor based on a Field programmable Gate Array (FPGA) is developed. The co-processor is suitable for efficient computation of nonlinear functions involved in typical soft computing techniques such as: activation functions (neural networks), membership functions (fuzzy systems), or kernel functions (support vector machines). The method is applied to the development of an intelligent embedded system for a smart scenario. Experimental results are provided for both online training and feed-forward computation of a single-layer feed-forward neural network.

A divide-and-conquer strategie for FPGA implementations of large MLP-based classifiers

This paper presents a methodology to implement large Neural Networks based classifiers in low-cost FPGAs. The idea is to divide the large Neural Network into several smaller networks which can easily be implemented in small devices. Then, a Multiple Classifier Ensemble is used to joint the results of each small network and thus provide the output of the system. To validate the proposal a classification experiment of terrain images of satellite has been developed and implemented. Obtained results related the size, velocity and performance of the implemented system confirm the viability of the methodology.