Raul Rammula

Impact of plasma treatment on electrical properties of TiO2/RuO2 based DRAM capacitor

In this work, we systematically studied the influence of the plasma treatment (PT) on the structural and electrical properties of Pt/rutile-TiO2/RuO2 metal–insulator–metal capacitors. The leakage current of the 12 nm thick TiO2 dielectrics prepared by atomic layer deposition was reduced below 10−7 A cm−2 while the capacitance equivalent thickness was kept below 0.5 nm using oxygen PT of the bottom RuO2 electrode. Reflection high energy electron diffraction, transmission electron microscopy, atomic force microscopy and x-ray photoelectron spectroscopy analyses allowed the conclusion that O2 plasma smoothened the RuO2 surface and increased its oxygen content through plasma induced surface reconstruction. The nucleation of TiO2 on the plasma-treated surface was faster while the thickness of the capacitor dead layer at the TiO2/RuO2 interface was reduced.

Nanoscale Characterization of TiO2 Films Grown by Atomic Layer Deposition on RuO2 Electrodes

Topography and leakage current maps of TiO2 films grown by atomic layer deposition on RuO2 electrodes using either a TiCl4 or a Ti(O-i-C3H7)4 precursor were characterized at nanoscale by conductive atomic force microscopy (CAFM). For both films, the leakage current flows mainly through elevated grains and not along grain boundaries. The overall CAFM leakage current is larger and more localized for the TiCl4-based films (0.63 nm capacitance equivalent oxide thickness, CET) compared to the Ti(O-i-C3H7)4-based films (0.68 nm CET). Both films have a physical thickness of ∼20 nm. The nanoscale leakage currents are consistent with macroscopic leakage currents from capacitor structures and are correlated with grain characteristics observed by topography maps and transmission electron microscopy as well as with X-ray diffraction.

Atomic layer deposition of aluminum oxide films on graphene

Seed-layer approach was studied to initiate atomic layer deposition (ALD) of Al2O3 films on graphene. Low-temperature ALD and electron beam evaporation (EBE) were applied for seed-layer preparation before deposition of the dielectric at 200 °C using trimethyl-aluminum and water or ozone as precursors. To characterize nucleation of the films and possible influence of the ALD processes on the quality of graphene, properties of graphene and Al2O3 films were investigated by Raman spectroscopy, X-ray fluorescence and X-ray photoelectron spectroscopy methods. The results suggest that seed layer formation by low-temperature ALD was more efficient in the O3-based process than in the H2O-based one while EBE seed layer provided fastest growth of Al2O3 together with minimum incubation period.

Atomic Layer Deposition of High-k Oxides on Graphene

Graphene that is a single hexagonal layer of carbon atoms with very high intrinsic charge carrier mobility (more than 200 000 cm2/Vs at 4.2 K for suspended samples; Bolotin, et al., 2008) attracts attention as a promising material for future nanoelectronics. During last few years, significant advancement has been made in preparation of large-area graphene. The lateral sizes of substrates for graphene layers have been increased up to 3⁄4 m (Bae et al., 2010) and continuous roll-to-roll deposition of graphene has been published (Hesjedal, 2011). This kind of progress might allow one to apply similar planar technologies for fabricating graphene-based devices in future as currently used for processing of siliconbased structures. After very first experiments (Novoselov et al., 2004), in which the electrical properties of isolated graphene sheets were characterized, a lot of attention has been paid to the similar studies, i.e. investigation of uncovered graphene flakes deposited on oxidized silicon wafers that served as back gates. However, in order to realize graphene-based devices, a highquality dielectric on top of graphene is required for electrostatic gates as well as for tunnel barriers for spin injection. For efficient control of charge carrier movement dielectric layers deposited on graphene should be very thin, a few nanometers thick, and of very uniform thickness without any pinholes. At the same time, the dielectric should possess high dielectric constant, high breakdown voltage and low leakage current even at a small thickness. And, of course, it is expected that the high mobility of charge carriers in graphene should not be markedly affected by the dielectric layer. In order to make top-gated graphene-based Field Effect Transistor (FET), Lemme et al. (2007) applied evaporation techniques for preparation of a gate stack with ~20 nm thick SiO2 dielectric layer on graphene. They used p-type Si(100) wafers with a boron doping concentration of 1015 cm-3, which were oxydized to a SiO2 thickness of 300 nm. On these wafers, micromechanically exfoliated graphene flakes were sticked. The Ti/Au source and drain electrodes were prepared using optical lift-off lithography. Next, electron beam lift-off lithography was applied to define a top gate electrode on top of the graphene flake covered with the dielectric (Fig. 1a). Lemme et al. were first to demonstrate that the combined effect of back and top gates can be applied to graphene devices. However, measurements of the back-gate characteristics before