Ravindran Mohanavelu

A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS

The last few years have witnessed a rapid increase in serial IO data rates as well as number of IO ports in microprocessors. This trend, poses significant challenges to the serial IO design because of area and power budget limitations but, above all, by the need to achieve stringent bit error rates in the presence of interconnect constraints such as channel loss, impedance discontinuities induced by package and connectors, and crosstalk effects due to routing limitations in the package and on the motherboard. To effectively meet these challenges, the serial IO architecture has evolved to include more complex equalization schemes. Building on the previous work on a 4-tap DFE [1], this paper presents the design of a complete serial IO capable of operating up to 11.8Gb/s, and in particular, focuses on the integration of an adaptive equalizer and baud-rate CDR in the receiver of the serial IO.

3.4 A 40/50/100Gb/s PAM-4 Ethernet transceiver in 28nm CMOS

High-speed signaling using NRZ has approached speeds above 50Gb/s where it is extremely difficult to maintain power efficiency and performance over a wide variety of channels and applications. PAM-4 is emerging as one way to increase throughput in such band-limited channels. Higher modulation formats help to address cost in optical systems by packing more bits/wavelength [1]. Strong momentum in standards to adopt PAM-4 reflects these significant trends in the industry. At the same time, migrating transceiver designs to current technology nodes have narrowed the power gap between traditional Analog and ADC-DSP-DAC-based systems for high-speed applications. These factors make ADC-based receivers a highly desirable choice, as is also the trend in wireless communications.

A novel 40-GHz flip-flop-based frequency divider in 0.18/spl mu/m CMOS

This paper presents a 40GHz flip-flop-based frequency divider incorporating a latch topology with two distinct tail current sources and an enabled cross-coupled pair during the tracking mode, to speed up the latch operation and to increase the driving capability. The proposed frequency divider performs at 40GHz without shunt or series peaking inductors. The circuit was fabricated in a 0.18/spl mu/m SiGe BiCMOS process provided by Jazz Semiconductor, where only CMOS transistors were used. It draws 5mA current from a 1.8V supply voltage.