Aaron K. Martin

An 8Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation and clock deskew

An 8Gb/s binary source-synchronous I/O link with adaptive receiver-equalization, offset cancellation and clock deskew is implemented in 0.13/spl mu/m CMOS. The analog equalizer is implemented as an 8-way interleaved, 4-tap discrete-time linear filter. On-die adaptation logic determines optimal receiver settings.

An 8-Gb/s simultaneous bidirectional link with on-die waveform capture

A full-duplex transceiver capable of 8-Gb/s data rates is implemented in 0.18-/spl mu/m CMOS. This equalized transceiver has been optimized for small area (329 /spl mu/m /spl times/ 395 /spl mu/m) and low power (158 mW) for point-to-point parallel links. Source-synchronous clocking and per-pin skew compensation eliminate coding bandwidth overhead and reduce latency, jitter, and complexity. This link is self-configuring through the use of automatic comparator offset trim and adaptive deskew. Comprehensive diagnostic capabilities have been integrated into the transceiver to provide link, interconnect, and circuit characterization without the use of external test equipment. With a resolution of 4 mV and 9 ps, these capabilities enable on-die eye diagram generation, equivalent time waveform capture, noise characterization, and jitter distribution measurements.

8Gb/s differential simultaneous bidirectional link with 4mV 9ps waveform capture diagnostic capability

Differential simultaneous bidirectional I/O circuits in 0.18 /spl mu/m CMOS operate up to 8 Gb/s with BER better than 10/sup -11/ using 32 b LFSR. The cell area is 0.13 mm/sup 2/ and the dissipation is 120 mW. On-die diagnostic measurement of individual I/O link performance is enabled with a variable offset comparator and clock phase interpolator with resolution of 4 mV and 9 ps.

5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family

The next-generation enterprise Xeon® server processor has 15 dual-threaded 64b Ivybridge cores [1] and 37.5MB shared L3 cache. The system interface includes two on-chip memory controllers, each with two memory channels and supports multiple system topologies. The processor has 4.31B transistors in a high-κ metal-gate tri-gate 22nm CMOS technology with 9 metal layers [2]. The design supports a wide array of product offerings with thermal design power ranging from 40 to 150W and frequencies ranging from 1.4 to 3.8GHz. Fig. 5.4.1(a) shows the processor block diagram. The floorplan (Fig. 5.4.1(b)) is driven by the ring bus routability and latency, as well as the chop requirements to smaller core counts. The cores and associated L3 cache are organized in columns of five, with the ring bus segment embedded. The fully populated die has 15-cores in three columns. The 10-core chop removes the rightmost 3rd column and its dedicated top and bottom IOs. CMOS muxes embedded in the ring bus are programmably operable in a 2-or-3-columns configuration. The 6-core chop removes the 2nd and 4th rows from the 10-core die.

A 22 nm 15-Core Enterprise Xeon® Processor Family

This paper describes a 4.3B transistors, 15-cores, 30-threads enterprise Xeon® processor with a 37.5 MB shared L3 cache implemented in a 22 nm 9M Hi-K metal gate tri-gate process. A modular floorplan methodology enables easy chops to 10 and 6 cores. Multiple clock and voltage domains are used to reduce power consumption. The clock distribution uses a single PLL per column to save power and minimize deskew crossing points. Integrated PCIe Gen3 and Quick Path Interconnect® (QPI) ports operate at 8GT/s. The 4-channel memory interface supports both 1866 MT/s DDR3 and a new memory buffer interface running at 2667 MT/s on the same pins. The core, cache and I/O recovery techniques improve manufacturing yields and enable multiple product flavors from the same silicon die.

A High-Frequency CMOS Current Summing Circuit

This work presents a signal summing circuit intended for application in a high-frequency linear equalizer. The circuit is capable of operating at frequencies reaching 10 GHz when implemented on a 0.18 μ CMOS process.

On-die supply-inducecd jitter behavioral modeling

This paper describes a simple, yet efficient supply-induced jitter modeling methodology for high-speed I/O circuits. The proposed model uses the average supply noise and a linear factor derived from Spice simulations to estimate the jitter for a circuit block. For circuits with bias voltages, the transfer function of the biasing network is included. The model is implemented in Simulink and closely correlated with Spice simulations. The modeling accuracy is further validated to be within ±15% of the silicon measurement for the period jitter of a ring oscillator. The jitter modeling technique is applied to multiple memory I/O designs and can be extended to other high-speed interface designs and their timing budgeting.