Ravindranath Naiknaware

Automated Hierarchical Cmos Analog Circuit Stack Generation with Intramodule Connectivity and Matching Considerations

An efficient automated layout for CMOS transistors in analog circuits is described. The matching requirements are used as the primary constraint on the analog layout; however, parasitic capacitances and area considerations are also included. A designer-chosen arbitrary circuit partition from the schematic can be used to generate the corresponding layout as an optimum stack of transistors with complete intramodule connectivity. The transistor stack generation is performed by representing the circuit with a diffusion graph and recursively fragmenting the graph until the base constructs are reached. For each of the modules, the port structures are also created. These port structures are considered as part of the module area and parasitic optimization procedure. With aspect-ratio-related constraints, the procedure allows optimal floorplanning. The results are demonstrated through several examples.

Process-insensitive low-power design of switched-capacitor integrators

A generalized analytical technique is developed to design power optimized switched-capacitor integrators taking process variations into account. It is shown that the performance of a robustly designed power optimum switched-capacitor integrator is a monotonic function of the slew rate and the transconductance of the amplifier. The framework provides an analytical solution for fabrication foundry independent analog design and therefore eliminates the need for Monte Carlo simulations to estimate the effect of the worst-case performance variations. With this analytical approach, it is possible to migrate the design to technologies with smaller feature sizes while obtaining monotonic improvement in the performance. The validity of the proposed analytical model for the design of robust switched-capacitor integrators is demonstrated through transistor-level SPICE simulations using BSIM3v3 models.

Power optimization of /spl Delta//spl Sigma/ analog-to-digital converters based on slewing and partial settling considerations

A technique to obtain low power /spl Delta//spl Sigma/ ADC designs under slewing and partial settling behavior of the integrators is described. /spl Delta//spl Sigma/ ADCs do not require complete settling of the integrators to the overall converter accuracy due to their oversampling and noise-shaping characteristics. When the slewing and incomplete settling behavior of the modulator are explored properly, it is possible to obtain power optimal designs. Accurate estimates are obtained under non-ideal conditions such as finite switch resistances in the sampling and the feedback paths. It is also shown that the noise reduction strategies such as correlated double sampling (CDS) significantly affect the power requirements.

CMOS analog circuit stack generation with matching constraints

An efficient CMOS transistor stack generation procedure for analog circuits is described. The matching requirements are used as the primary constraint on the analog layout, however, parasitic capacitances and area considerations are also included. A designer chosen arbitrary circuit partition from the schematic can be used to generate the corresponding layout as an optimum stack of transistors with complete intra-module connectivity. The port structures are considered as part of the module area and parasitic optimization procedure. The results are demonstrated through an example and a complete chip layout of a high-resolution delta-sigma analog-to-digital converter.

Switched-capacitor integrator design optimizing for power and process variations

When the slewing and small-signal settling behavior of switched-capacitor integrators are explored properly, it becomes possible to obtain power optimal designs. However, in order to obtain robust designs with slewing behavior, the process variations have to be carefully considered. An analytical technique is developed to obtain power optimum design of switched-capacitor integrators with process variations consideration. The technique provides the worst and best ease estimates and obviates the need for Monte-Carlo simulations. We demonstrate the approach by providing performance variations of optimized integrators in a 0.6 /spl mu/m CMOS process.

142 dB /spl Delta//spl Sigma/ ADC with a 100 nV LSB in a 3 V CMOS process

A /spl Delta//spl Sigma/ ADC designed in a 0.6 /spl mu/m CMOS process uses a reference voltage of only 1.0 V to provide a dynamic range of 142 dB and 132 dB in a bandwidth of 100 and 1000 Hz, respectively. The power optimized ADC implemented using a noise cancellation strategy has a noise floor of -168 dB, equivalent to the noise of a 1 k/spl Omega/ resistor. A reference ADC designed without a noise reduction mechanism has a noise floor of -148 dB. The high resolution converter targeted for sensitive instrumentation such as remote seismic monitoring and biomedical devices consumes 22.8 mW from a single 3.0 V supply.

Schematic driven module generation for analog circuits with performance optimization and matching considerations

A technology independent correct-by-construction module generation for analog circuits is described. The designer selects an arbitrary analog circuit partition in the schematic, and the procedure generates the corresponding layout as a optimal stack of transistors with complete intra-module connectivity. The matching requirements are used as the primary constraint along with considerations for parasitics, aspect-ratio, and area. For each of the modules, the port structures are also created for simplified routing. Corresponding to the selected circuit partition, a fully parameterized design rule independent module is generated. Any changes in the schematic and the design rules are automatically reflected in each of the modules. Results are demonstrated through a test chip.

Time-referenced single-path multi-bit /spl Delta//spl Sigma/ ADC using a VCO based quantizer

In this paper, we present a novel single-path multi-bit delta-sigma analog-to-digital converter (/spl Delta//spl Sigma/ ADC) architecture that uses time as a reference for performing multi-bit digital-to analog conversion in the feedback path. The architecture uses a voltage-controlled oscillator (VCO) as a multi-bit quantizer. In the feedback path of the /spl Delta//spl Sigma/ ADC, the errors due to component mismatch are avoided by using a single-path for all the levels in a multi bit digital to-analog converter (DAC). The technique eliminates the need for feedback DAC architectures with static and dynamic component matching.

Architectural coefficient synthesis for the implementation of optimal higher-order /spl Delta//spl Sigma/ analog-to-digital converters

This paper describes a method to synthesize architectural coefficients for higher-order /spl Delta//spl Sigma/ modulators. Considerations for maximum dynamic range and optimal power are addressed. First, a modulator with optimal theoretical performance is synthesized. Then, the theoretical /spl Delta//spl Sigma/ ADC is scaled to make it realizable with maximum dynamic range, and finally, the modulator is further modified for optimal power and area performance. During each of the steps, the modulator theoretical performance and stability characteristics are preserved. Construction of an optimal seventh-order modulator is demonstrated. It is also shown that the coefficient synthesis significantly affects the power and area consumption.