Terri S. Fiez

Linearity enhancement of multibit /spl Delta//spl Sigma/ A/D and D/A converters using data weighted averaging

A dynamic element matching algorithm, data weighted averaging, is introduced for use in multibit /spl Delta//spl Sigma/ data converters. Using this algorithm, distortion spectra from DAC linearity errors are shaped by first-order noise shaping, resulting in a dynamic range improvement of 9 dB/octave when DAC errors dominate. Combining this technique with random dithering nearly eliminates the aliasing of the DAC errors into the baseband. Simulations show that with only 1% element matching 110 dB signal-to-noise ratio (18 b) is achieved for a third-order 3-b modulator with an oversampling ratio of 128.

Efficient Far-Field Radio Frequency Energy Harvesting for Passively Powered Sensor Networks

An RF-DC power conversion system is designed to efficiently convert far-field RF energy to DC voltages at very low received power and voltages. Passive rectifier circuits are designed in a 0.25 mum CMOS technology using floating gate transistors as rectifying diodes. The 36-stage rectifier can rectify input voltages as low as 50 mV with a voltage gain of 6.4 and operates with received power as low as 5.5 muW(22.6 dBm). Optimized for far field, the circuit operates at a distance of 44 m from a 4 W EIRP source. The high voltage range achieved at low load current make it ideal for use in passively powered sensor networks.

Piezoelectric micro-power generation interface circuits

New power conversion circuits to interface to a piezoelectric micro-power generator have been fabricated and tested. Circuit designs and measurement results are presented for a half-wave synchronous rectifier with voltage doubler, a full-wave synchronous rectifier and a passive full-wave rectifier circuit connected to the piezoelectric micro-power generator. The measured power efficiency of the synchronous rectifier and voltage doubler circuit fabricated in a 0.35-/spl mu/m CMOS process is 88% and the output power exceeds 2.5 /spl mu/W with a 100-k/spl Omega/, 100-nF load. The two full-wave rectifiers (passive and synchronous) were fabricated in a 0.25-/spl mu/m CMOS process. The measured peak power efficiency for the passive full-wave rectifier circuit is 66% with a 220-k/spl Omega/ load and supplies a peak output power of 16 /spl mu/W with a 68-k/spl Omega/ load. Although the active full-wave synchronous rectifier requires quiescent current for operation, it has a higher peak efficiency of 86% with an 82-k/spl Omega/ load, and also exhibits a higher peak power of 22 /spl mu/W with a 68-k/spl Omega/ load which is 37% higher than the passive full-wave rectifier.

Switched-current circuit design issues

Switched-current (SI) circuits represent a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. Unlike switched-capacitor (SC) circuits, SI circuits require only a standard digital CMOS process. SI circuits use MOS transistors as the storage elements to provide analog memory capability. Similar to the operation of dynamic logic circuits, a voltage is sampled onto the gate of a MOSFET and held on its noncritical gate capacitance. The held voltage signal on the gate causes a corresponding held current signal in the drain, usually proportional to the square of the gate-to-source voltage. Design issues related to the implementation and performance of SI circuits are presented. SI filters show comparable performance to SC filters except in terms of passband accuracy. The major source of error is nonunity current gain in the SI integrator due to device mismatch and clock-feedthrough effects. For the initial CMOS prototypes, the current track and hold (T/H) gain error was about 2.5%. >

A scalable substrate noise coupling model for design of mixed-signal IC's

This paper describes a design-oriented scalable macromodel for substrate noise coupling in heavily-doped substrates. The model requires only four parameters which can be readily extracted from a small number of device simulations or measurements. Once these parameters have been determined, the model can be used in design for any spacing between the injection and sensing contacts and for different contact geometries. The scalability of the model with separation and width provides insight into substrate coupling and optimization issues prior to and during the layout phase. The model is validated with measurements from test structures fabricated in a 0.5 /spl mu/m CMOS process. Applications of the model to circuit design are demonstrated with simulation results.

CMOS switched-current ladder filters

The design and implementation of switched-current (SI) ladder filters is described. The basic current-mode circuits, including the SI differential integrator/summer are developed. The SI integrator/summer is shown to be directly analogous to the switched-capacitor (SC) integrator/summer; thus, all the synthesis techniques developed for the design of SC filters can be used to synthesize SI filters. Signal flowgraph synthesis of SI ladder filters is presented. The nonideal characteristics of SI ladder filters that limit their accuracy are evaluated. Clock-feedthrough and device mismatch induced errors are more severe in the present SI circuit configurations than in SC circuits. A standard digital 2- mu m n-well CMOS process has been used to implement two high-order ladder filters. Simulations accurately predict the measured results of the first integrated SI filters. The area and power dissipation are comparable to those obtained with the switched-capacitor technique. >

A 14 Bit Continuous-Time Delta-Sigma A/D Modulator With 2.5 MHz Signal Bandwidth

A continuous-time delta-sigma A/D modulator with 5 MS/s output rate in a 2.5 V 0.25 mum CMOS process is presented. The modulator has a fifth-order single-stage, dual-loop architecture allowing nearly one clock period quantizer delay. A multi-bit quantizer is used to increase resolution and multi-bit non-return-to-zero DACs are adopted to reduce clock jitter sensitivity. Capacitor tuning is utilized to overcome loop coefficient shifts due to process variations. Self-calibration is implemented to suppress current-steering DAC mismatch. Clocked at 60 MHz, the prototype chip achieves 81 dB peak SNR and 85 dB dynamic range with a 12X oversampling ratio. The power consumption is 50 mW.

Novel power conditioning circuits for piezoelectric micropower generators

Low power devices promote the development of micropower generators (MPGs). This paper presents a novel power conditioning circuit (PCC) that enables maximum power extraction from a piezoelectric MPG. Synchronous rectification (SR) is employed to improve the PCC efficiency. A simplified model of the piezoelectric generator is developed for simulation. Performance of the proposed PCC is verified by PSpice simulation and experimental results. A maximum output power of 18.8 /spl mu/W has been extracted from a single piezoelectric MPG. Arbitrary waveform generator representation (AWGR) of the flexing piezoelectric membrane is also presented. The hardware AWGR enables research on the PCC without the need for the actual MPG heat engine or bulge tester used to flex the piezoelectric membrane, and also demonstrates the feasibility of cascading many MPGs to extract additional power.

Current-feedthrough effects and cancellation techniques in switched-current circuits

Distortion due to device mismatches and clock-feedthrough in switched-current circuits is analyzed. A replication-based current feedthrough cancellation technique that reduces the clock-feedthrough current more than 20 dB is proposed. SPICE simulation results for this circuit are given.<<ETX>>

A CMOS transconductor with 80-dB SFDR up to 10 MHz

A CMOS transconductor uses resistors at the input and an OTA in unity-gain feedback to achieve 80-dB spurious-free dynamic range (SFDR) for 3.6-V/sub pp/ differential inputs up to 10 MHz. The combination of resistors at the input and negative feedback around the operational transconductance amplifier (OTA) allows this transconductor to accommodate a differential input swing of 4 V with a 3.3-V supply. The total harmonic distortion (THD) of the transconductor is -77 dB at 10 MHz for a 3.6-V/sub pp/ differential input and third-order intermodulation spurs measure less than -79 dBe for 1.8-V/sub pp/ differential inputs at 1 MHz. The transconductance core dissipates 10.56 mW from a 3.3-V supply and occupies 0.4 mm/sup 2/ in a 0.35-/spl mu/m CMOS process.