Ray A. Bittner

A phone-centered body sensor network platform cost, energy efficiency & user interface

We have designed a Bluetooth-based body sensor network platform for physiological diary applications and have addressed its challenges in cost, energy efficiency, and user interface. In our platform, an Internet-capable phone serves as the center and manages every network member. We designed a Bluetooth sensor node for general sensing devices to join the network without much alteration. Since Bluetooth imposes a large power overhead, we have taken extreme care to minimize its duty cycle. We also incorporated a wrist-worn device as the user interface. It displays information under the instruction of the phone in an ambient fashion, and enables the user to interact with the network conveniently. By leveraging resources on the phone, we are able to minimize the cost and energy consumption of the sensor nodes and the wrist-worn device

A Non-invasive Wearable Neck-Cuff System for Real-Time Sleep Monitoring

Sleep is an important part of our lives which affects many life factors such as memory, learning, metabolism and the immune system. Researchers have found correlations between sleep and several diseases such as Chronic Obstructive Pulmonary disease, Chronic Heart Failure, Alzheimers disease, etc. However, sleep data is mainly recorded and diagnosed in sleep labs or in hospitals for some critical cases with high costs. In this work we develop a non-invasive, wearable neck-cuff system capable of real-time monitoring and visualization of physiological signals. These signals are generated from various sensors housed in a soft neck-worn collar and sent via Bluetooth to a cell phone which stores the data. This data is processed and reported to the user or uploaded to the cloud and/or to a local PC. With this system we are able to monitor peoples sleep continuously in a non-invasive and low cost method while at the same time collect a large database for sleep data which may benefit future advances in new findings and possibly enable a diagnosis of other diseases. We show as one of the applications of our system the possible detection of obstructive sleep apnea which is a common sleep disorder.

Computing kernels implemented with a wormhole RTR CCM

The wormhole run-time reconfiguration (RTR) computing paradigm is a method for creating high performance computational pipelines. The scalability, distributed control and data flow features of the paradigm allow it to fit neatly into the configurable computing machine (CCM) domain. To date, the field has been dominated by large bit-oriented devices whose flexibility can lead to lowered silicon utilization efficiencies. In an effort to raise this efficiency, the Colt CCM has been created based on the wormhole RTR paradigm. This paper outlines methods of implementation and performance for several common operations using these concepts. They serve as indicators of the diversity of algorithms that can be instantiated through the high-speed run-time reconfiguration that these devices make possible. Particular attention is paid to floating point multiplication. Also discussed is the topic of data dependent computation which would seem to be counter intuitive to the wormhole RTR paradigm. The paper concludes with a summary of performance of the three computations.

Direct GPU/FPGA communication Via PCI express

We describe a mechanism for connecting GPU and FPGA devices directly via the PCI Express bus, enabling the transfer of data between these heterogeneous computing units without the intermediate use of system memory. We evaluate the performance benefits of this approach over a range of transfer sizes, and demonstrate its utility in a computer vision application. We find that bypassing system memory yields improvements as high as 2.2× in data transfer speed, and 1.9× in application performance.

Colt: an experiment in wormhole run-time reconfiguration

Wormhole run-time reconfiguration (RTR) is an attempt to create a refined computing paradigm for high performance computational tasks. By combining concepts from field programmable gate array (FPGA) technologies with data flow computing, the Colt/Stallion architecture achieves high utilization of hardware resources, and facilitates rapid run-time reconfiguration. Targeted mainly at DSP-type operations, the Colt integrated circuit -- a prototype wormhole RTR device -- compares favorably to contemporary DSP alternatives in terms of silicon area consumed per unit computation and in computing performance. Although emphasis has been placed on signal processing applications, general purpose computation has not been overlooked. Colt is a prototype that defines an architecture not only at the chip level but also in terms of an overall system design. As this system is realized, the concept of wormhole RTR will be applied to numerical computation and DSP applications including those common to image processing, communications systems, digital filters, acoustic processing, real-time control systems and simulation acceleration.

Random decision tree body part recognition using FPGAs

Random decision tree classification is used in a variety of applications, from speech recognition to Web search engines. Decision trees are used in the Microsoft Kinect vision pipeline to recognize human body parts and gestures for a more natural computer-user interface. Tree-based classification can be taxing, both in terms of computational load and memory bandwidth. This makes highly-optimized hardware implementations attractive, particularly given the strict power and form factor limitations of embedded or mobile platforms. In this paper we present a complete architecture that interfaces the Kinect depth-image sensor to an FPGA-based implementation of the Forest Fire pixel classification algorithm. Key performance parameters, algorithmic improvements and design trade-off are discussed.

Speedy bus mastering PCI express

PCI Express is a ubiquitous bus interface providing the highest bandwidth connection in the PC platform. Sadly, support for it in FPGAs is limited and/or expensive. The Speedy PCIe core addresses this problem by bridging the gap from the bare bones interface to a user friendly, high performance design. This paper describes some of the fundamental design challenges and how they were addressed as well as giving detailed results. The hardware and software source code are available for free download from [12].

Direct GPU/FPGA Communication via PCI Express

Parallel processing has hit mainstream computing in the form of CPUs, GPUs and FPGAs. While explorations proceed with all three platforms individually and with the CPU-GPU pair, little exploration has been performed with the synergy of GPU-FPGA. This is due in part to the cumbersome nature of communication between the two. This paper presents a mechanism for direct GPU-FPGA communication and characterizes its performance in a full hardware implementation.

Bus mastering PCI express in an FPGA

This paper describes a bus mastering implementation of the PCI Express protocol using a Xilinx FPGA. While the theoretical peak performance of PCI Express is quite high, attaining that performance is a complex endeavor on top of an already complex protocol. The implementation is described and its performance is analyzed. Source code is offered for free download via the web.

FPGA side-channel receivers

The popularity of FPGAs is rapidly growing due to the unique advantages that they offer. However, their distinctive features also raise new questions concerning the security and communication capabilities of an FPGA-based hardware platform. In this paper, we explore the some of the limits of FPGA side-channel communication. Specifically, we identify a previously unexplored capability that significantly increases both the potential benefits and risks associated with side-channel communication on an FPGA: an in-device receiver. We designed and implemented three new communication mechanisms: speed modulation, timing modulation and pin hijacking. These non-traditional interfacing techniques have the potential to provide reliable communication with an estimated maximum bandwidth of 3.3 bit/sec, 8 Kbits/sec, and 3.4 Mbits/sec, respectively.