Ray Beffa

Self-test of a memory device

Wafer level burn-in of memory integrated circuits

Apparatus and method implementing repairs on a memory device

Apparatus and method for testing for defects between memory cells in packaged semiconductor memory devices

Data compression circuit and method for testing memory devices

Self-test circuit for memory integrated circuits

Method and apparatus for testing an integrated circuit including the step/means for storing an associated test identifier in association with integrated circuit identifier for each test to be performed on the integrated circuit

Method and apparatus for testing of dielectric defects in a packaged semiconductor memory device

System for stressing a memory integrated circuit die

Method of stress testing memory integrated circuits