Ray Simar

The TMS320C30 floating-point digital signal processor

The 320C30 is a fast processor with a large memory space and floating-point-arithmetic capabilities. The authors describe the 320C30 architecture in detail, discussing both the internal organization of the device and the external interfaces. They also explain the pipeline structure, addressing software-related issues and constructs, and examine the development tools and support. Finally, they present examples of applications. Some of the major features of the 320C30 are: a 60-ns cycle time that results in execution of over 16 million instructions per second (MIPS) and over 33 million floating-point operations per second (Mflops); 32-bit data buses and 24-bit address buses for a 16M-word overall memory space; dual-access, 4 K*32-bit on-chip ROM and 2 K*32-bit on-chip RAM; a 64*32-bit program cache; a 32-bit integer/40-bit floating-point multiplier and ALU; eight extended-precision registers, eight auxiliary registers, and 23 control and status registers; generally single-cycle instructions; integer, floating-point, and logical operation; two- and three-operand instructions; an on-chip DMA controller; and fabrication in 1- mu m CMOS technology and packaging in a 180-pin package. These facilitate FIR (finite impulse response) and IIR (infinite impulse response) filtering, telecommunications and speech applications, and graphics and image processing applications.<<ETX>>

Floating-point processors join forces in parallel processing architectures

The hardware architecture and software capabilities of the TMS320C40 floating-point digital signal processor are described. The C40 operates at 275 million operations per second (MOPS) and transfers data at a rate of 320 Mbytes/s with a 40-ns cycle time. A key architectural feature of the C40 for parallel computing is the six parallel bidirectional communication ports that permit direct connection and communication between processors in a parallel system. Examples illustrating the use of the C40 in a parallel processing environment are discussed.<<ETX>>

Codevelopment of the TMS320C6X VelociTI architecture and compiler

Continuing dramatic improvements in semiconductor manufacturing processes are enabling radical new signal processing architectures at the chip level. The development of these new architectures must be coupled with clearly defined target applications, a thorough analysis of applicable signal processing algorithms, and significant advancements in code-generation technology. The TMS320C6x development program involved the codevelopment of the VelociTI architecture, a new code-generation capability, and a large set of representative benchmarks.

DSP architectures, algorithms, and code-generation: fission or fusion?

Continuing dramatic improvements in semiconductor manufacturing processes are enabling radical new signal-processing architectures at the chip level. But how do we ensure that the radical becomes practical? The development of these new architectures must be coupled, a fusion, with clearly defined target applications, a thorough analysis of applicable signal processing algorithms, and significant advancements in code-generation technology. The TMS320C6x development program involved the codevelopment of the VelociTI architecture, a new code-generation environment, and a large set of representative benchmarks.

The TMS320C40: a DSP for parallel processing

The TMS320C40 is the first parallel-processing general-purpose DSP. The TMS320C40 architecture combines six communication ports for direct processor-to-processor communication, a six-channel DMA coprocessor for concurrent I/O, a high-performance DSP CPU, memory, program cache, 32-bit global and local memory buses, two timers and an analysis module. This level of monolithic integration allows the TMS320C40 to achieve 275 MOPS (million operations per second) and 320 Mbytes per second of I/O.<<ETX>>

The Changing Impact of Semiconductor Technology on Processor Architecture

We stand on the brink of a fundamental discontinuity in silicon process-technology unlike anything most of us have seen. For almost two decades, a period of time spanning the entire education and careers of many engineers, we have been beneficiaries of a silicon process-technology which would let us build almost anything we could imagine. Now, all of that is about to change. For the past five years, capacitive loading of interconnect has grown to be a significant factor in logic speed, and has limited the scaling of integrated-circuit performance. To compound the problem, recently interconnect resistance has also started to limit circuit speed. These factors can render obsolete current designs and current thinking as interconnect-dominated designs and architectures will become increasingly irrelevant. Given these fundamental interconnect challenges, we must turn to architecture, logic design and programming solutions. The background on these dramatic changes in semiconductor technology will be discussed in the hopes that the solutions for the future may very well come from the attendees of HPCC 2007!

Of Processors and Processing

Digital signal processing is a stealth technology. It is the core enabling technology in everything from your cellphone to the Mars Rover. It goes much further than just enabling a one-time breakthrough product. It provides ever-increasing capability; compare the performance gains made by dial-up modems with the recent performance gains of DSL and cable modems. Remarkably, digital signal processing has become ubiquitous with little fanfare, and most of its users are not even aware of what it is. Therefore, it is worthwhile to look at the development history of DSP, an explanation of what the technology is, and a review of the many technologies that are used to implement modern digital signal processing systems.

A parametric elliptical arc algorithm

Publisher Summary Sometimes an arc of a circle or of an ellipse is a better choice than a cubic spline for representing a particular curved shape. Circles and ellipses are inherently simpler curves than cubics, so the algorithms for generating them should also be simpler. This is chiefly why conic splines are popular in applications such as the generation of font outlines, where drawing speed is of critical importance. This chapter describes an algorithm for generating points along an elliptical arc. The points are separated by a fixed angular increment specified in radians of elliptical arc. The algorithm is based on a parametric representation of the ellipse. It is particularly inexpensive in terms of the amount of computation required. Only a few integer shifts, additions, and subtractions are needed to generate each point—without compromising accuracy. Defining an ellipse in terms of its conjugate diameters is equivalent to defining the ellipse in terms of an enclosing parallelogram. The chapter illustrates affine transformation of a unit circle inscribed in a square into an ellipse inscribed in a parallelogram.

A step toward real-time interactive FIR filter design

This paper outlines the development of a new tool for the digital signal processing engineer. The coupling of a frequency sampling technique for the design of linear-phase FIR filters with recent advances in digital signal processors has led to the development of a real-time interactive FIR filter design technique. The system accepts samples of the desired frequency response as inputs, determines the corresponding linear-phase FIR filter, and implements the filter. This allows the DSP engineer to adjust the filter while simultaneously examining its response to an input signal. The input signal might be a test signal derived from a spectrum analyzer, an audio signal, or any general signal source of interest. This flexibility provides the user with what will hopefully be a valuable tool in a broad variety of digital signal processing applications. The simplicity and utility of the system is further emphasized by the implementation of the system on a single Texas Instruments TMS32010 digital signal processor.