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Dive into the research topics where Raymond B. Essick is active.

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Featured researches published by Raymond B. Essick.


intelligent vehicles symposium | 2005

RSVP II: a next generation automotive vector processor

Silviu Chiricescu; S. Chai; Kent D. Moat; Brian G. Lucas; P. May; J. Norm; Raymond B. Essick; Michael A. Schuette

A large number of sensors (i.e., video, radar, laser, ultrasound, etc.) that continuously monitor the environment are finding their way in the average automobile. The algorithms processing the data captured by these sensors are streaming in nature and require a high rate of computation. Due to the characteristics of the automotive environment, this computation has to be delivered under very low energy and cost budgets. The reconfigurable streaming vector processing (RSVP/spl trade/) architecture is a vector coprocessor architecture which accelerates streaming data processing. This paper presents the RSVP architecture and its second implementation, RSVP II. Our results show significant speedups on data streaming functions running compiled code. On a lane tracking application, RSVP II shows impressive performance results. From a performance/


ieee intelligent vehicles symposium | 2004

RSVP/spl trade/: an automotive vector processor

Silviu Chiricescu; Michael A. Schuette; Raymond B. Essick; Brian G. Lucas; P. May; Kent D. Moat; J. Norris

and performance/mW perspective, RSVP architecture compares favorably with leading DSP architectures. The time to market is substantially reduced due to ease of programmability, elimination of hand-tuned assembly code, and support for software re-use through binary compatibility across multiple implementations.


Archive | 2002

Streaming vector processor with reconfigurable interconnection switch

Brian G. Lucas; Philip E. May; Kent D. Moat; Raymond B. Essick; Silviu Chiricescu; James M. Norris; Michael A. Schuette; Ali Saidi

A myriad of sensors (i.e., video, radar, laser, ultrasound, etc.) continuously monitoring the environment are incorporated in future automobiles. The algorithms processing the data captured by these sensors are streaming in nature and require high levels of processing power. Due to the characteristics of the automotive market, this processing power has to be delivered under very low energy and cost budgets. The Reconfigurable Streaming Vector Processing (RSVP/spl trade/) is a vector coprocessor architecture which accelerates streaming data processing. This paper presents the RSVP architecture, programming model, and a first implementation. Our results show significant speedups on data streaming functions. Running compiled code, RSVP outperforms an ARM9 host processor on average by a factor of 31 on a set of kernels. From a performance/


Archive | 2003

Partitioned vector processing

James M. Norris; Philip E. May; Kent D. Moat; Raymond B. Essick; Brian Geoffrey Lucas

and performance/mW perspective, RSVP compares favorably with leading DSP architectures. The time to market is substantially reduced due to ease of programmability, elimination of hand-tuned assembly code, and support for software re-use through binary compatibility across multiple implementations.


Archive | 2006

SYSTEM FOR OVERRIDING INTREPRETED BYTE-CODE WITH NATIVE CODE

Mark A. Patel; Steve R. Bunch; Raymond B. Essick


Archive | 2004

Queuing cache for vectors with elements in predictable order

Kent D. Moat; Raymond B. Essick; Philip E. May; James M. Norris


Archive | 2004

Method and apparatus for parallel computations with incomplete input operands

Raymond B. Essick; Brian Geoffrey Lucas


Archive | 2002

Method of programming linear graphs for streaming vector computation

Philip E. May; Kent D. Moat; Raymond B. Essick; Silviu Chiricescu; Brian G. Lucas; James M. Norris; Michael A. Schuette; Ali Saidi


Archive | 2003

Data processing system using multiple addressing modes for SIMD operations and method thereof

William C. Moyer; James M. Norris; Philip E. May; Kent D. Moat; Raymond B. Essick; Brian Geoffrey Lucas


Archive | 2008

Method and apparatus for nested instruction looping using implicit predicates

Raymond B. Essick; Kent D. Moat; Michael A. Schuette

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