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Dive into the research topics where Silviu Chiricescu is active.

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Featured researches published by Silviu Chiricescu.


IEEE Design & Test of Computers | 1998

Rothko: a three-dimensional FPGA

Miriam Leeser; Waleed Meleis; Mankuan Michael Vai; Silviu Chiricescu; Weidong Xu; Paul M. Zavracky

Using transferred circuits and metal interconnections placed between layers of active devices anywhere on the chip, Rothko aims at solving utilization, routing, and delay problems of existing FPGA architectures. Experimental implementations have demonstrated important performance advantages.


IEEE Transactions on Very Large Scale Integration Systems | 2001

Design and analysis of a dynamically reconfigurable three-dimensional FPGA

Silviu Chiricescu; Miriam Leeser; Mankuan Michael Vai

This paper presents the design and analysis of a dynamically reconfigurable field programmable gate array (FPGA) that consists of three physical layers: routing and logic block layer, routing layer, and memory layer. The architecture was developed using a methodology that examines different architectural parameters and how they affect different performance criteria such as speed, area, and reconfiguration time. The resulting architecture has high performance while the requirement of balancing the areas of its constituent layers is satisfied.


IEEE Communications Magazine | 2005

Streaming processors for next-generation mobile imaging applications

Sek M. Chai; Silviu Chiricescu; Ray Essick; Brian Lucas; Phil May; Kent D. Moat; J. Norris; Mike Schuette; Abelardo López-Lagunas

Next-generation mobile devices will continue to demand high processing power for imaging applications. The expected performance is in the class of supercomputers, but delivered with limited energy and memory bandwidth for embedded systems. This article advocates a streaming computation model that leverages the deterministic access patterns in imaging applications to deliver the necessary processing throughput. A reconfigurable datapath connects a set of functional units, forming a computation pipeline to offer energy efficiency. The architecture and implementation of a stream processor are presented along with the memory subsystem to support stream data transfers. The results show speedup ranging from a factor of 2 to 28 for imaging applications, offering favorable comparison against scalar processors.


intelligent vehicles symposium | 2005

RSVP II: a next generation automotive vector processor

Silviu Chiricescu; S. Chai; Kent D. Moat; Brian G. Lucas; P. May; J. Norm; Raymond B. Essick; Michael A. Schuette

A large number of sensors (i.e., video, radar, laser, ultrasound, etc.) that continuously monitor the environment are finding their way in the average automobile. The algorithms processing the data captured by these sensors are streaming in nature and require a high rate of computation. Due to the characteristics of the automotive environment, this computation has to be delivered under very low energy and cost budgets. The reconfigurable streaming vector processing (RSVP/spl trade/) architecture is a vector coprocessor architecture which accelerates streaming data processing. This paper presents the RSVP architecture and its second implementation, RSVP II. Our results show significant speedups on data streaming functions running compiled code. On a lane tracking application, RSVP II shows impressive performance results. From a performance/


local computer networks | 2009

Battery-aware localization in wireless networks

Ali Saidi; Chuntao Zhang; Silviu Chiricescu; Loren J. Rittle; Yang Yu

and performance/mW perspective, RSVP architecture compares favorably with leading DSP architectures. The time to market is substantially reduced due to ease of programmability, elimination of hand-tuned assembly code, and support for software re-use through binary compatibility across multiple implementations.


ieee intelligent vehicles symposium | 2004

RSVP/spl trade/: an automotive vector processor

Silviu Chiricescu; Michael A. Schuette; Raymond B. Essick; Brian G. Lucas; P. May; Kent D. Moat; J. Norris

An important mechanism to conserve energy and extend the battery life of low-power wireless networks is to increase the sleep-cycle of the nodes. However, increasing sleep-cycles can have unintended consequences on the application performance. Therefore, it is important to understand the impact of various sleep-cycle parameters on the performance of any given application. In this paper, we analyze the relationship between the sleep-cycle period and the accuracy of the localization application. We show that the sleep-cycle period has an exponential relationship with many of the parameters that impact localization accuracy. In general, such relationships lend themselves especially well to energy efficient system-level design of location dependent applications. Finally, to demonstrate the validity of our analysis, using an IEEE 802.11 based localization system, we present a set of experimental results that show the relationships between the sleep-cycle and the measurements accuracies in the localization systems.


field programmable logic and applications | 2002

Morphable Multipliers

Silviu Chiricescu; Michael A. Schuette; Robin Glinton; Herman Schmit

A myriad of sensors (i.e., video, radar, laser, ultrasound, etc.) continuously monitoring the environment are incorporated in future automobiles. The algorithms processing the data captured by these sensors are streaming in nature and require high levels of processing power. Due to the characteristics of the automotive market, this processing power has to be delivered under very low energy and cost budgets. The Reconfigurable Streaming Vector Processing (RSVP/spl trade/) is a vector coprocessor architecture which accelerates streaming data processing. This paper presents the RSVP architecture, programming model, and a first implementation. Our results show significant speedups on data streaming functions. Running compiled code, RSVP outperforms an ARM9 host processor on average by a factor of 31 on a set of kernels. From a performance/


Archive | 2002

Streaming vector processor with reconfigurable interconnection switch

Brian G. Lucas; Philip E. May; Kent D. Moat; Raymond B. Essick; Silviu Chiricescu; James M. Norris; Michael A. Schuette; Ali Saidi

and performance/mW perspective, RSVP compares favorably with leading DSP architectures. The time to market is substantially reduced due to ease of programmability, elimination of hand-tuned assembly code, and support for software re-use through binary compatibility across multiple implementations.


Archive | 2007

METHOD AND SYSTEM FOR GAS LEAK DETECTION AND LOCALIZATION

Ali Saidi; Silviu Chiricescu; James M. Norris; Michael A. Schuette


Archive | 2002

Method of programming linear graphs for streaming vector computation

Philip E. May; Kent D. Moat; Raymond B. Essick; Silviu Chiricescu; Brian G. Lucas; James M. Norris; Michael A. Schuette; Ali Saidi

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