Raymond E. Barnett

A RF to DC Voltage Conversion Model for Multi-Stage Rectifiers in UHF RFID Transponders

This paper presents a RF to DC conversion model for multi-stage rectifiers in UHF RFID transponders. An equation relating the RF power available from the antenna to the DC output voltage produced by a multi-stage rectifier is presented. The proposed model includes effects of the nonlinear forward voltage drop in diodes and impedance matching conditions of the antenna to rectifier interface. Fundamental frequency impedance approximation is used to analyze the resistance of rectifying diodes; parasitic resistive loss components are also included in the analysis of rectifier input resistance. The closed form equation shows insights into design parameter tradeoffs, such as power available from the antenna, antenna radiation resistance, the number of diodes, DC load current, parasitic resistive loss components, diode and capacitor sizes, and frequency of operation. Therefore, it enables the optimization of rectifier parameters for impedance matching with a low-cost printed antenna and shunt tuning inductor, in order to improve the RF to DC conversion efficiency and the operational distance of UHF RFID transponders. Three diode doublers and three multistage rectifiers were fabricated in a 130 nm CMOS process with custom no-mask added Schottky diodes. Measurements of the test IC are in good agreement with the proposed model.

A 110 nA Voltage Regulator System With Dynamic Bandwidth Boosting for RFID Systems

This paper describes a voltage regulator system for ultra-low-power RFID tags (also called passive tags) in a 0.15 mum analog CMOS technology. These tags derive their power supply from the incoming RF energy through rectification instead of from a battery. The regulator is functional with just 110 nA current. Owing to the huge variation of the rectified voltage (by as much as tens of volts), voltage limiters and clamps are employed at various points along the regulation path. A limiter at the rectifier output clamps the rectifier voltage to a narrower range of 1.4 V. A fine-regulator, then, regulates the supply voltage close to a bandgap reference value of 1.25 V. The key aspect of this regulator is the dynamic bandwidth boosting that takes place in the regulator by sensing the excess current that is bypassed in the limter (during periods of excess energy) and increasing its bias current and hence bandwidth, accordingly. A higher bandwidth is necessary for quick recovery from line transients due to the burst nature of RF transmission, with a larger energy burst requiring a higher bandwidth to settle quickly without large line transients. The challenge of compensating such a regulator across various load currents and RF energy levels is described in this paper

A Passive UHF RFID Transponder for EPC Gen 2 with -14dBm Sensitivity in 0.13μm CMOS

A passive RFID transponder conforming to the EPC Gen 2 standard is presented, including an RF and analog front-end, EEPROM, and a digital processing core and features a unique RF sampled analog random number generator to support the required anti-collision protocol. Fabricated in 0.13mum CMOS, the 0.55mm2 IC functions at a sensitivity of -14dBm using an 860-to-960MHz carrier at 40-to-160kb/s RX data rates.

A 440-nA True Random Number Generator for Passive RFID Tags

This paper describes a 440-nA true random number (RN) generator for passive ultrahigh frequency radio frequency identification (RFID) tags that operate in the 900-MHz band. Since passive tags derive their power supply through the rectification of the incoming RF signal, limited power is available, and hence, a typical total IC current budget is less than a few microamperes. An RN is generated by a passive RFID tag on the fly, and it is used by the reader to identify the tag uniquely and communicate with it in a field consisting of many tags. The RN in this paper consists of a 16-bit-long deterministic binary sequence to which a 3-bit true RN is added. Without the 3-bit true RN, if two tags happen to have the same deterministic 16-bit sequence, a collision occurs, and there is no way to resolve it. In this paper, we propose a power efficient way of generating the 3-bit true RN using the jitter-sampled carrier technique. This technique subsamples the already present 900-MHz RF carrier using a jittered (noisy) clock. The design challenges of sampling a high-frequency signal that swings above and below ground are described. In addition, the generation of a jitter of adequate magnitude with adequate high-frequency spectral content to ensure that the number is truly random is also described. Measurement results on a silicon prototype implemented in a 130-nm analog CMOS process are provided.

An EEPROM Programming Controller for Passive UHF RFID Transponders With Gated Clock Regulation Loop and Current Surge Control

This paper presents an EEPROM programming controller imbedded in a passive UHF RFID transponder. A 14 V programming voltage is generated and regulated for a 224-bit EEPROM memory array from a rectified voltage supply of 2-3 V. A gated clock regulation loop is proposed to keep the programming voltage constant over a wide range of received RF input power, in order to improve the write-erase endurance of the memory. A current surge control scheme is proposed to allow the EEPROM programming voltage ramping in steps, therefore, preventing the collapse of the rectified supply in the remotely powered transponder. Also presented is a nano-power switched bandgap reference to reduce die area through the reduction of MOmega resistors needed for nano-power operation. Measurement results show that a 0.35 mum CMOS transponder IC provides a stable EEPROM programming voltage which varies less than 8% over a large 30 dB input power range while consuming 7 muW. The EEPROM programming controller occupies 0.092 mm2 die area.

A 0.8V 1.52MHz MSVC Relaxation Oscillator with Inverted Mirror Feedback Reference for UHF RFID

A 0.8V nano-power relaxation oscillator for EPC standard UHF RFID transponder is presented. A low-voltage inverted mirror feedback VGS/R reference is proposed to provide correlated current and voltage references for the oscillator. As a result, the oscillator frequency is solely determined by the resistor in the reference and the timing capacitor to meet the frequency tolerance specification. Meanwhile, to minimize the power consumption, a minimum-supply-voltage-constraint (MSVC) design criterion is proposed to minimize the required supply voltage. The inverted mirror feedback technique reduces the headroom requirement of the traditional VGS /R to meet the MSVC. Measurement results show that the entire oscillator requires a minimum supply voltage of 0.8V in the prototype chip fabricated in CMOS 0.13mum technologies. The measured oscillation frequency is 1.52MHz with 400nA total current consumption. The chip area is 13400mum2

Design of multistage rectifiers with low-cost impedance matching for passive RFID tags

The paper presents analysis of the input impedance, as well as the input capacitance and output resistance of diode doublers and multistage rectifiers. Tradeoffs between device sizes and the number of rectification stages are presented with an emphasis on low cost impedance matching. As a result, it is possible to achieve higher efficiency in RF to DC conversion with low cost impedance matching by using just a strap inductor between the antenna and the rectifier IC. Four diode doublers and three multistage rectifiers have been designed and fabricated using a 0.13mum CMOS process with EEPROM. Measurement results are in agreement with the analysis

A Passive UHF RFID Demodulator With RF Overvoltage Protection and Automatic Weighted Threshold Adjustment

This paper presents a passive UHF RFID ASK demodulator that operates over a +24 dBm to -14 dBm RF input power range. The demodulator automatically adjusts between high sensitivity mode for weak RF signal power and overvoltage protection mode for high RF power. The input overvoltage protection circuit is designed to protect the IC from high input power while not impacting the sensitivity at weak input power. The demodulator is comprised of a RF rectifier, a variable gain attenuator with automatic threshold adjustment and a nano-power data slicer. The demodulator handles demodulating signals with a minimum to maximum envelope ratio of 0.8 over the entire input power range, and the data slicer consumes only 160 nA from a 0.9 to 1.25 V rectified supply. The RFID chip is fabricated in a 0.13 μm analog-CMOS technology and the entire chip occupies an area of 0.55 mm2.

An EEPROM Programming Controller for Passive UHF RFID Transponders with Gated Clock Regulation Loop and Current Surge Control

This paper presents an EEPROM programming controller imbedded in a passive UHF RFID transponder. It generates a 14 V programming voltage for a 224-bit EEPROM memory array from a rectified voltage supply of 2-3 V. A gated clock regulation loop is proposed to keep the programming voltage constant over a wide range of received RF input power, in order to improve the write-erase endurance of the memory. A current surge control scheme is proposed to allow the EEPROM programming voltage ramping in steps, therefore, preventing the collapse of the rectified supply in the remotely powered transponder. Also presented is a nano-power switched bandgap reference to reduce die area through the reduction of Meg-ohm resistors needed for nano-power operation. Measurement results show that a 0.35 mum CMOS transponder IC provides a stable 14 V EEPROM programming voltage and consumes only 7 muW during write operation. The EEPROM programming controller occupies 0.092 mm2 die area.

A high dynamic range ASK demodulator for passive UHF RFID with automatic over-voltage protection and detection threshold adjustment

This paper presents a passive UHF RFID ASK demodulator that operates over a +24dBm to −14dBm RF input power range. The demodulator automatically adjusts between high sensitivity mode for weak RF signal power and over-voltage protection mode for high RF power. The input over-voltage protection circuit is designed to protect the IC from high input power while not impacting the sensitivity at weak input power. The demodulator is comprised of a RF rectifier, a variable gain attenuator with automatic threshold adjustment and a nano-power data slicer. The demodulator handles demodulating signals with a minimum to maximum envelope ratio of 0.8 over the entire input power range, and the data slicer consumes only 160nA from a 0.9 to 1.25V rectified supply. The RFID chip is fabricated in a 0.13µm analog-CMOS technology and the entire chip occupies an area of 0.55 mm2.