Ganesh K. Balachandran

A 110 nA Voltage Regulator System With Dynamic Bandwidth Boosting for RFID Systems

This paper describes a voltage regulator system for ultra-low-power RFID tags (also called passive tags) in a 0.15 mum analog CMOS technology. These tags derive their power supply from the incoming RF energy through rectification instead of from a battery. The regulator is functional with just 110 nA current. Owing to the huge variation of the rectified voltage (by as much as tens of volts), voltage limiters and clamps are employed at various points along the regulation path. A limiter at the rectifier output clamps the rectifier voltage to a narrower range of 1.4 V. A fine-regulator, then, regulates the supply voltage close to a bandgap reference value of 1.25 V. The key aspect of this regulator is the dynamic bandwidth boosting that takes place in the regulator by sensing the excess current that is bypassed in the limter (during periods of excess energy) and increasing its bias current and hence bandwidth, accordingly. A higher bandwidth is necessary for quick recovery from line transients due to the burst nature of RF transmission, with a larger energy burst requiring a higher bandwidth to settle quickly without large line transients. The challenge of compensating such a regulator across various load currents and RF energy levels is described in this paper

A Passive UHF RFID Transponder for EPC Gen 2 with -14dBm Sensitivity in 0.13μm CMOS

A passive RFID transponder conforming to the EPC Gen 2 standard is presented, including an RF and analog front-end, EEPROM, and a digital processing core and features a unique RF sampled analog random number generator to support the required anti-collision protocol. Fabricated in 0.13mum CMOS, the 0.55mm2 IC functions at a sensitivity of -14dBm using an 860-to-960MHz carrier at 40-to-160kb/s RX data rates.

A 440-nA True Random Number Generator for Passive RFID Tags

This paper describes a 440-nA true random number (RN) generator for passive ultrahigh frequency radio frequency identification (RFID) tags that operate in the 900-MHz band. Since passive tags derive their power supply through the rectification of the incoming RF signal, limited power is available, and hence, a typical total IC current budget is less than a few microamperes. An RN is generated by a passive RFID tag on the fly, and it is used by the reader to identify the tag uniquely and communicate with it in a field consisting of many tags. The RN in this paper consists of a 16-bit-long deterministic binary sequence to which a 3-bit true RN is added. Without the 3-bit true RN, if two tags happen to have the same deterministic 16-bit sequence, a collision occurs, and there is no way to resolve it. In this paper, we propose a power efficient way of generating the 3-bit true RN using the jitter-sampled carrier technique. This technique subsamples the already present 900-MHz RF carrier using a jittered (noisy) clock. The design challenges of sampling a high-frequency signal that swings above and below ground are described. In addition, the generation of a jitter of adequate magnitude with adequate high-frequency spectral content to ensure that the number is truly random is also described. Measurement results on a silicon prototype implemented in a 130-nm analog CMOS process are provided.

A 1.16mW 69dB SNR (1.2MHz BW) continuous time £Δ ADC with immunity to clock jitter

A low-power jitter tolerant 2nd order active-passive continuous-time sigma-delta ADC in 65nm CMOS is presented. The use of just one active Gm-C integrator and a feed-forward path from the ADCs input to the Gms output helps reduce power consumption. A FIR filter in the outermost feedback path reduces clock jitter impact. For a −2dBFS input, the ADC clocked at 300MHz achieves a 69dB SNR (10KHz – 1.2MHz BW) while consuming 1.16mW from a 1.4V supply.

A high dynamic range ASK demodulator for passive UHF RFID with automatic over-voltage protection and detection threshold adjustment

This paper presents a passive UHF RFID ASK demodulator that operates over a +24dBm to −14dBm RF input power range. The demodulator automatically adjusts between high sensitivity mode for weak RF signal power and over-voltage protection mode for high RF power. The input over-voltage protection circuit is designed to protect the IC from high input power while not impacting the sensitivity at weak input power. The demodulator is comprised of a RF rectifier, a variable gain attenuator with automatic threshold adjustment and a nano-power data slicer. The demodulator handles demodulating signals with a minimum to maximum envelope ratio of 0.8 over the entire input power range, and the data slicer consumes only 160nA from a 0.9 to 1.25V rectified supply. The RFID chip is fabricated in a 0.13µm analog-CMOS technology and the entire chip occupies an area of 0.55 mm2.

Power management subsystem with bi-directional DC to DC converter for μ-power biomedical applications

This paper presents a power management subsystem for μ-power biomedical applications. The power management subsystem is embedded in a wireless sensor SoC that requires 1.5V to operate, with the exception of the sensor bias and RF transmitter which require 3V. The proposed power management block can accept a 3V coin cell or 1.5V button cell battery to operate the entire IC. A bi-directional DC/DC converter is implemented such that 3V can be generated from a 1.5V battery, or, alternately, a 1.5V power supply, can be generated from a 3V battery. When using a 1.5V battery the forward mode DC/DC converter generates a 3V supply with 97% efficiency, while in the reverse mode the 3V supply generates a 1.5V supply with 95% efficiency. The circuit is specially designed to be highly efficient with micro-power loads up to 60µW. The power management circuit is comprised of a bi-directional DC/DC converter or Charge Pump, Charge Pump Startup Circuit, Real Time Clock (RTC), Power On reset (POR), micro power bandgap, analog temperature circuit, 6 degree C temperature comparator, LDO, ADC reference and sensor reference. The circuit is fabricated in a 0.35µm BCD technology and occupies an area of 1.125 mm2.