Raymond E. Siferd

CMOS VLSI implementation of a low-power logarithmic converter

We present a unique 32-bit binary-to-binary logarithm converter including its CMOS VLSI implementation. The converter is implemented using combinational logic only and it calculates a logarithm approximation in a single clock cycle. Unlike other complex logarithm correcting algorithms, three unique algorithms are developed and implemented with low-power and fast circuits that reduce the maximum percent errors that result from binary-to-binary logarithm conversion to 0.9299 percent, 0.4314 percent, and 0.1538 percent. Fast 4, 16, and 32-bit leading-one detector circuits are designed to obtain the leading-one position of an input binary word. A 32-word/spl times/5-bit MOS ROM is used to provide 5-bit integers based on the corresponding leading-one position. Both converter area and speed have been considered in the design approach, resulting in the use of a very efficient 32-bit logarithmic shifter in the 32-bit logarithmic converter. The converter is implemented using 0.6/spl mu/m CMOS technology, and it requires 1,600/spl lambda//spl times/2,800/spl lambda/ of chip area. Simulations of the CMOS design for the 32-bit logarithmic converter, operating at V/sub DD/ equal to 5 volts, run at 55 MHz, and the converter consumes 20 milliwatts.

A fast, low-power logarithm approximation with CMOS VLSI implementation

A new technique and CMOS VLSI implementation for computing approximate logarithms (base 2,and 10) for binary integers is presented. The approximation is performed using only combinational logic and requires no multiplications. Additionally, as implemented, a ROM of only N/spl times/log/sub 2/(N) bits is used to convert N bit integers. The maximum error of the approximation is 1.5% when the input value is 3, and decays exponentially to less than 0.5% for input values greater than 25.

VLSI implementation of a low-power antilogarithmic converter

This paper presents a VLSI implementation of a unique 32-bit antilogarithmic converter, which generates data for some digital-signal-processing (DSP) applications. Novel antilogarithm correcting algorithms are developed and implemented with low-power and hardware-efficient correcting circuits. The VLSI implementations of these algorithms are much smaller than other hardware intensive algorithms found in the literature. The converter is implemented using 0.6 /spl mu/m CMOS technology, and its combinational logic implementation requires 1500/spl lambda//spl times/2800/spl lambda/ of chip area. The 32-bit antilogarithmic converter computes the antilogarithm in a single clock cycle and runs at 100 MHz and consumes 81 mW.

Quaternary logic circuits in 2- mu m CMOS technology

Novel quaternary logic circuits, designed in 2- mu m CMOS technology, are presented. These include threshold detector circuits with an improved output voltage swing and a simple binary-to-quaternary encoder circuit. Based on these, the literal circuits, the quaternary-to-binary decoder, and the quaternary register are derived. A novel scheme for improving the power-delay product of pseudo-NMOS circuits is developed. Simulations for an inverter indicate a 66% improvement over a conventional pseudo-NMOS circuit. Noise-margin and tolerance estimations are made for the threshold detectors. To demonstrate the utility of these circuits, a quaternary sequential/storage logic array (QSLA), based on the Allen-Givone algebra has been designed and fabricated. The prototype chip occupies an area of 4.84 mm/sup 2/, is timed with a 2.2-MHz clock, and consumes 93 mW of power. >

Low power sigma delta decimation filter

This paper presents an efficient design and implementation of a low power sigma delta digital decimation filter. We implement a low power decimation filter with a narrow transition finite impulse response (FIR) filter using a canonic signed digit number (CSD) system. We use multi-stage multi-rate signal processing to design and implement half-band filters and narrow transition band FIR filters. The decimation filter is designed using Simulink, DSP Blockset and simulated using Matlab. The FIR filter has been coded in Verilog and implemented using FPGA Xilinx 4000 technology. The power consumption of the proposed decimation filter is reduced by 67% compared to the conventional 4-stage comb-FIR architecture.

CMOS VLSI implementation of 16-bit logarithm and anti-logarithm converters

This paper presents two unique 16-bit binary-to-binary logarithm and binary logarithm-to-binary converters including their CMOS VLSI implementations. Both converters are implemented using combinational logic only, and they calculate Mitchells logarithm and anti-logarithm approximations in a single clock cycle. Simulations of the 0.6 /spl mu/ CMOS design for the logarithm and anti-logarithm converters ran at 150 and 178 MHz, respectively. A novel leading one detector circuit is designed to obtain the leading one position.

High Performance CMOS Analog Arithmetic Circuits

Unique designs for CMOS analog arithmetic circuits are presented which perform addition (V1 + V2), subtraction (V2 − V1), add/invert −(V1 + V2), and multiply (V1 × V2). The circuit operation is based on the inherent square law of MOS transistor drain current when operating in the saturation region. Key features include: good linearity and accuracy, single ended voltage inputs and output, wide input and output range and no input bias voltages. The circuits can be directly coupled (no buffer) and serve as basic building blocks for analog signal processing implementations such as analog filters and adaptive equalizers. All circuits were implemented in 1.2 μm CMOS technology.

A doughnut layout style for improved switching speed with CMOS VLSI gates

A doughnut style for physical layout of CMOS gates which improves the switching speed of the gates compared to a standard layout style is discussed. This improvement in performance is obtained by decreasing the self-loading output capacitance for a given W/L ratio of the transistor channels. A design for a 30-bit incrementer which was fabricated and tested as a 3- mu m VLSI circuit is included as an example of an application for the doughnut-style gates. The incrementer has a propagation delay of less than 10 ns through nine stages of logic gates with large fan-outs at three of the stages. >

CMOS VLSI implementation of a digital logarithmic multiplier

A fast multiplier based on the logarithmic number system is implemented in a VLSI chip. Multiplication in the decimal number system is equivalent to an addition in the logarithmic number system, thus, the use of logarithms reduce the operation of multiplication to simple addition. Multiplication of two binary numbers can be achieved by adding the binary logarithms of the two numbers and then deriving the antilog of the result. The approximate logarithm of a binary number can be found from the number itself through a process of shifts and counting. This is a simpler design process as compared to storing the logarithms on an on-chip ROM which results in complex hardware as the word length increases. The logarithmic approximation results in some error in the product. This is reduced using an error reduction technique. The presence of error limits the application of this multiplier to applications in signal processing where it is not critical. The design is implemented using a 2.0 micron double metal process.

Identifiability of nonlinear dynamical systems

This paper considers identifiability of a class of nonlinear systems described by {x(t) = f[t, x(t), u(t), ¿]; x(to) = xo} and associated nonlinear discrete observation process y(ti) = h[x(ti), u(ti), ¿]. Sufficient conditions for local and global identifiability of parameters ¿ are established for deterministic systems and noiseless observations.