Shailesh B. Nerurkar

Low-power decimator design using approximated linear-phase N-band IIR filter

This correspondence presents a new design of a low-power decimation filter, which consists of a poly-phase finite-impulse-response (FIR)-4 comb filter, an approximate linear-phase one-third-band infinite-impulse-response (IIR) filter, and a half-band FIR filter. A poly-phase FIR-4 comb filter architecture was designed, which consumes 75% less power than the recursive comb filter architecture. New general equations were derived for the design of 1/N-band IIR filters, and these equations were used to design a novel approximate linear-phase one-third-band IIR filter. The decimation filter is designed using Simulink and DSP Blockset, and Matlab simulations are performed to verify the phase linearity and magnitude response of the designed filter. The group delay for the passband region of one-third-band IIR filter has a negligible error of 0.009%. The resulting decimation filter has 60% less hardware and consumes 67% less power than the comb-FIR-FIR decimation filter.

Low power sigma delta decimation filter

This paper presents an efficient design and implementation of a low power sigma delta digital decimation filter. We implement a low power decimation filter with a narrow transition finite impulse response (FIR) filter using a canonic signed digit number (CSD) system. We use multi-stage multi-rate signal processing to design and implement half-band filters and narrow transition band FIR filters. The decimation filter is designed using Simulink, DSP Blockset and simulated using Matlab. The FIR filter has been coded in Verilog and implemented using FPGA Xilinx 4000 technology. The power consumption of the proposed decimation filter is reduced by 67% compared to the conventional 4-stage comb-FIR architecture.

High speed digital filter design using minimal signed digit representation

This paper presents the design and implementation of novel decimation filter structure for high speed asymmetric digital subscriber line (ADSL). Existing ADSL circuits use comb-FIR-FIR decimation filter structures, which have low throughput, more hardware and high power consumption. Unlike existing ADSL circuits, we design a novel high speed filter architecture and implement it using the minimal signed digit (MSD) representation. The MSD representation is suitable for common subexpression elimination, and it significantly reduces the number of adders required for the filter synthesis. Each digital-filter structure is simulated using Matlab, and its complete architecture is captured using DSP Blockset and Simulink. The resulting filter architecture has higher throughput, less hardware and consumes less power than the comb-FIR-FIR and comb-IIR-FIR architectures. The filter has been implemented on Xilinx FPGA using Virtex-2 technology. Compared to the comb-FIR-FIR and the comb-IIR-FIR architectures, the designed decimation filter architecture contributes to a hardware saving of 82% and 74%, respectively; in addition, it reduces the power dissipation by 91% and 79%, respectively.

Design and implementation of a decimation filter for hearing aid applications

In this paper we deal with the design and implementation of a decimation filter used for hearing aid applications. We implement the decimation filter using the canonic signed digit (CSD) representation. Each digital filter structure is simulated using Matlab, and its complete architecture is captured using DSP Blockset and Simulink. The filter has been implemented on Xilinx FPGA using Virtex-2 technology. The resulting architecture is hardware efficient and consumes less power compared to conventional decimation filters. Compared to the comb-FIR-FIR architecture, the designed decimation filter architecture contributes to a hardware saving of 69%; in addition, it reduces the power dissipation by 83%, respectively.

High speed flash analog-to-digital converter

In this paper, we design a pipelined flash ADC to achieve high speed of 2 GHz in 0.18 mum CMOS technology using Cadence design tools. We design a high speed track and hold and a novel thermometer to binary encoder. We considered several approaches to design the track and hold circuit, such as buffered track and hold, switched capacitor track and hold, and single tail track and hold. These circuits are slower or have stability problems. We have used a current mode dual array track and hold, which is not only stable but also ensures good performance at 2 GHz. The thermometer to binary encoder can be designed using fat tree encoder, differential cascade voltage switch using pass gate encoder and ROM encoder with pass gates. We implement a novel encoder, which has advantages of high speed and hardware reduction over existing encoder circuits. A clocked DCVSPG XOR gate and a quantum voltage comparator are also used to improve the speed of the proposed flash ADC

Design and Implementation of a Decimation Filter For High Performance Audio Applications

In this paper, we deal with the design and practical implementation of a decimation filter used for high performance audio applications. We implemented the decimation filter using the canonic signed digit (CSD) representation. The decimation filter was simulated using Matlab, and its complete architecture was realized using DSP Blockset and Simulink. The filter was implemented using Mentor Graphic ModelSim and Calibre Tool in FPGA technology. The resulting architecture is hardware efficient and consumes less power compared to conventional decimation filters. Compared to the comb-FIR-FIR-FIR architecture, the designed decimation filter architecture contributes to a hardware saving of 69 %; in addition, it reduces the power dissipation by 28 %, respectively.

Linearization techniques in power amplifiers for 1.9 GHZ wireless transmitters

We considered power amplifier (PA) linearization techniques, such as the Cartesian feedback, the feed-forward, and Ying technique and evaluated their effects on the performance of 1.9 GHz wireless transmitters. We implemented the single step transmitter, the two step transmitter and the PLL based transmitter architectures in 0.18 mum CMOS technology. We modified and implemented a two-stage power amplifier, which consists of class F driver with class E power amplifier used as load instead of the conventional class E power amplifier with a buffer. The use of the modified two-stage power amplifier with Ying linearization technique in the PLL based transmitter architecture has achieved the best results when compared to designs based on other linearization techniques and other transmitter architectures. In the designed PLL transmitter, the power amplifiers 1 dB compression point has increased to 24.5 dBm, and this is about 25 % higher than the result obtained by a design based on the conventional class E power amplifier with the buffer

Implementation of a low power decimation filter using 1/3-band IIR filter

This paper presents a unique design and implementation of a low power decimation filter. The designed decimation filter architecture shows how the 1/3-band IIR filter and a poly-phase half-band FIR filter are used multirate multistage signal processing. The 1/3-band IIR filter is realized using six first order all-pass filters. Each filter stage is simulated using Matlab and, the complete architecture of the decimation filter is captured using Simulink and a DSP blockset. The hardware realization of the decimation filter is obtained using FPGA Xilinx technology. The designed decimation filter reduces the hardware by 59% and the power dissipation by 34% compared to conventional decimation filters.

Hardware efficient narrow band FIR filter

This paper presents a novel approach to implement a narrow band Finite Impulse Response (FIR) digital filter that requires less hardware than traditional FIR filter implementations. The hardware efficient Canonic Signed Digit (CSD) multiplier is used instead of the conventional multiplier to reduce the hardware. The digital filter has been initially designed using Simulink, DSP Blockset and has been tested for the required frequency response using Matlab. The FIR filter has been modeled and verified using Verilog HDL and is implemented using FPGA Xilinx 4000 technology. The use of the multistage multirate approach for the design of the FIR filter stages results in a hardware saving of about 80%.

Low power and hardware efficient decimation filter

This paper presents a novel implementation of low power and hardware efficient digital decimation filter. We use multi-stage multi-rate signal processing to design and implement poly-phase half-band FIR filters and a band-pass IIR filter. The band-pass IIR filter is realized by cascading six second order all-pass filters. The decimation filter is designed and simulated using Simulink, DSP blockset and Matlab. The hardware realization of the decimation filter is obtained using FPGA Xilinx technology. The resulting decimation filter has a power reduction of 42% and a hardware saving of 61% compared to conventional decimation filters.