Reinhard Exel

Limits of synchronization accuracy using hardware support in IEEE 1588

Clock synchronization protocols for packet-oriented networks, like IEEE 1588, depend on time stamps drawn from a local clock at distinct points in time. Due to the fact that software-generated time stamps suffer from jitter caused by non-deterministic execution times, many implementations for high precision clock synchronization rely on hardware support. This allows time readings for packets with very low jitter close to the physical layer. Nevertheless, approaches using hardware support have to carefully consider influences on synchronization accuracy when it comes to the range of nanoseconds. Among others, limits come from the update interval, oscillator stability, or hardware clock frequency. This paper enlightens the limits for such implementations based on an analysis of the influences of the main factors for jitter. The conclusions give hints for efficiently optimizing current implementations.

Delay and Jitter Characterization for Software-Based Clock Synchronization Over WLAN Using PTP

In distributed systems, clock synchronization performance is hampered by delays and jitter accumulated not only in the network, but also in the timestamping procedures of the devices being synchronized. This is particularly critical in software timestamp-based synchronization where both software- and hardware-related sources contribute to this behavior. Usually, these synchronization impairments are collapsed into a black-box performance figure without quantifying the impact of each individual source, which obscures the picture and reduces the possibility to find optimized remedies. In this study, for the first time, the individual sources of delay and jitter are investigated for an IEEE 802.11 wireless local area network (WLAN) synchronization system using the IEEE 1588 protocol and software timestamps. Novel measurement techniques are proposed to quantify the hardware- and software-related delay and jitter mechanisms. It is shown that the delays and their associated jitter originate from both the WLAN chipset and the host computer. Moreover, the delay from the chipset cannot be considered symmetric and any such assumption inevitably leads to a residual offset, and thus to synchronization inaccuracy. Therefore, a calibration-based approach is proposed to compensate for these delays and to improve the performance of WLAN synchronization. Experimental results show that with optimal error compensation, a similar synchronization performance as software-based synchronization in Ethernet networks can be achieved.

Localisation of Wireless LAN Nodes Using Accurate TDoA Measurements

Time based localisation methods like GPS are widely used for outdoor navigation, whereas indoor navigation is typically performed only on a cell-basis or based on the Received Signal Strength Indicator. Since RSSI is not able to fulfil all current requirements, Time of Arrival and Time Difference of Arrival based approaches have recently gained focus. As time based localisation has high demands on the quality of the timestamps, we propose a special receiver architecture for IEEE802.11b capable of a timestamping accuracy in the sub-nanosecond range. The receivers operation is demonstrated by an FPGA based wireless physical layer device implementation. Experimental results show an improvement in terms of accuracy by a factor of 100 up to 1000 over COTS wireless LAN hardware. This enables accurate localisation in wireless LANs just by adding of timing receivers.

Mitigation of Asymmetric Link Delays in IEEE 1588 Clock Synchronization Systems

The IEEE 1588 standard defines the Precision Time Protocol (PTP) which provides mechanisms for synchronizing distributed clocks in packet-based networks. The accuracy of PTP synchronization depends on a number of factors such as the quality of the timestamps, packet delay variation, clock stability, and the asymmetry. In the latest update of the standard, IEEE 1588 version 2008, compensations for asymmetric delays have been introduced into the protocol. However, specific procedures for determining the asymmetry have not been specified. This paper analyzes various asymmetry mitigation measures for software timestamping and proposes a timestamp correction-based asymmetry compensation scheme. Measurements using WLAN synchronization hardware show that the proposed scheme can almost mitigate the link asymmetry without requiring any changes in PTP or additional messages.

Improved clock synchronization accuracy through optimized servo parametrization

Slave servo clocks are of essential importance to maintain synchronization between the grandmaster and its associated slaves. The servo structure and parametrization should ideally achieve fast settling times, minimize the clock jitter, and keep the clock offset below a predefined boundary. Commonly used solutions for this challenge are adder-based clocks or voltage controlled oscillators together with proportional-integral (PI) controllers. This paper shows how to capture and calculate the impairments relevant for the servo clocks, in particular the oscillator wander. Based on these data we show that proper parametrization of the PI controller is the key for minimizing the clock offset to the grandmaster.

Impact of hard-and software timestamping on clock synchronization performance over IEEE 802.11

The possibility of equipping devices on the factory floor with wireless communication has brought up new applications and challenges. Among one of these challenges is clock synchronization which is required for easy network management and monitoring. The IEEE 802.11v amendment to IEEE 802.11 has opened the doors for establishing clock synchronization in industrial applications by providing mechanisms and guidelines for synchronization. This work addresses the synchronization means provided by the IEEE 802.11 standard, including the ones mentioned by IEEE 802.11v, and analyses the impact of both software and hardware timestamps on the synchronization performance through test-bed implementations. The results indicate that there are several elements which can affect the quality of both software and hardware time-stamps, which in turn affect the synchronization performance. Moreover, it is also shown that the timestamping accuracy itself is only one factor, and other factors such as control loop settings and synchronization interval also affect the final synchronization performance over WLAN.

Highly Accurate Timestamping for Ethernet-Based Clock Synchronization

It is not only for test and measurement of great importance to synchronize clocks of networked devices to timely coordinate data acquisition. In this context the seek for high accuracy in Ethernet-based clock synchronization has been significantly supported by enhancements to the Network Time Protocol (NTP) and the introduction of the Precision Time Protocol (PTP). The latter was even applied to instrumentation and measurement applications through the introduction of LXI. These protocols are usually implemented in software; however, the synchronization accuracy can only substantially be improved by hardware which supports drawing of precise event timestamps. Especially, the quality of the timestamps for ingress and egress synchronization packets has a major influence on the achievable performance of a distributed measurement or control system. This paper analyzes the influence of jitter sources remaining despite hardware support and proposes enhanced methods for up to now unmatched timestamping accuracy in Ethernet-based synchronization protocols. The methods shown in this paper reach sub-nanosecond accuracy, which is proven in theory and practice.

Asymmetry Mitigation in IEEE 802.3 Ethernet for High-Accuracy Clock Synchronization

Clock synchronization is one of the basic services in a distributed network as it enables a palette of services, such as synchronized measurements and actions, or time-based access to shared communication media. The IEEE 1588 standard defines the precision time protocol (PTP) that is capable of synchronizing multiple slave clocks to a master by means of synchronization event messages. Supported by the recent advances in hardware timestamping, PTP devices are ready for achieving synchronization accuracies in the subnanosecond range. The accuracy of practical synchronization systems is, however, often bounded by the inability to determine and compensate for asymmetric line delays leading to unresolvable clock offsets. Although IEEE 1588 version 2008 is able to compensate for known asymmetry, no specific measures to estimate the asymmetry are defined in the standard. In this paper, we present a solution to determine the asymmetry for 100Base-TX networks based on line swapping and highly accurate timestamping. When the presented approach is used within the startup procedure of an Ethernet link, the synchronization offsets can be minimized while the operation of the network is not impaired. We show by an FPGA-based prototype system that our approach is able to reduce the clock offset from multiple nanoseconds to below 120 ps.

Boundaries of Ethernet layer 2 hardware timestamping

Synchronizing clocks in a distributed system is an indeed challenging task. Although there exists a various class of applications, like synchronizing the clock of a PC with the network time protocol, where an accuracy of several milliseconds is sufficient, many applications, such as synchronized test and measurement or localization services in wireless LANs require a higher confidentiality in the time domain. This paper enlights some of the key restrictions and possibilities in the case of IEEE 802.3 Ethernet. As this case not only challenges the state of the art oscillator models, but also timestamping techniques, a novel, highly accurate approach for that is proposed. Moreover, a highly accurate deterministic approach also concerns the behavior of the physical layer devices and their influence on the asymmetry, as well as the underlying control loops an analysis of the behavior of both is given together with some preliminary results for Ethernet based clock synchronization in the nanosecond range.

Servo design for improved performance in software timestamping-assisted WLAN synchronization using IEEE 1588

The clock servo is an essential constituent of distributed clock synchronization systems and a determining factor for the synchronization performance. This paper focuses on the clock servo design for better accuracy and precision in software-based clock synchronization over WLAN. The behaviour of the clock servo is analysed in this work and errors arising from software timestamps and the oscillator are evaluated. These errors are then used to investigate the operating conditions of the servo loop which results in the least synchronization offset and jitter. Results are obtained through simulations and then verified experimentally by a prototypical implementation. The results indicate that the synchronization performance is optimal when the servo relies more on the oscillator and less on the software timestamps.