Thomas Bigler

Asymmetry Mitigation in IEEE 802.3 Ethernet for High-Accuracy Clock Synchronization

Clock synchronization is one of the basic services in a distributed network as it enables a palette of services, such as synchronized measurements and actions, or time-based access to shared communication media. The IEEE 1588 standard defines the precision time protocol (PTP) that is capable of synchronizing multiple slave clocks to a master by means of synchronization event messages. Supported by the recent advances in hardware timestamping, PTP devices are ready for achieving synchronization accuracies in the subnanosecond range. The accuracy of practical synchronization systems is, however, often bounded by the inability to determine and compensate for asymmetric line delays leading to unresolvable clock offsets. Although IEEE 1588 version 2008 is able to compensate for known asymmetry, no specific measures to estimate the asymmetry are defined in the standard. In this paper, we present a solution to determine the asymmetry for 100Base-TX networks based on line swapping and highly accurate timestamping. When the presented approach is used within the startup procedure of an Ethernet link, the synchronization offsets can be minimized while the operation of the network is not impaired. We show by an FPGA-based prototype system that our approach is able to reduce the clock offset from multiple nanoseconds to below 120 ps.

On clock synchronization over wireless LAN using timing advertisement mechanism and TSF timers

The most recent version of the IEEE 802.11 standard, 802.11-2012 has extended the means of clock synchronization for wireless LANs. One of the mechanisms in the standard is called timing advertisement (TA). It involves calculating and maintaining the time offset with respect to the timing synchronization function (TSF) timer of the access point (AP). In the wireless stations, the TSF-based synchronization mechanism and the offset is combined to establish synchronization to an external timebase. However, such a method provides only loose synchronization unless the skew estimate between the external time source and the TSF timer of the AP is also conveyed to the nodes in the network, for which the standard provides no support. This study, in turn, provides another method, which is called SyncTSF, in which the external clocks at the AP and the nodes are synchronized to their respective TSF timers. Through analysis and measurements, it is shown that both SyncTSF and TA-based synchronization are limited by the frequency skews between the TSF timers of the AP and the nodes. Hence, for these methods to offer good synchronization accuracy, a mechanism to distribute frequency skews from the AP to the nodes should be provided.

Synchronizing an IEEE 1588 slave clock over both paths of a redundant Ethernet system

It is expected that there is only a single active path between an IEEE 1588 master and slave. This is based on the general operation scenario of an Ethernet network, which depends on a setup without network loops. In a redundant Ethernet system based on the Parallel Redundancy Protocol (PRP) or the High availability Seamless Redundancy protocol (HSR), this expectation is skewed. There are two simultaneously active paths between an IEEE 1588 master and slave clock in these systems. Selecting the better path for synchronization, by applying additional qualification criteria in the best master clock algorithm, e.g., the correction field, is a common solution for this problem. This paper proposes a solution to use both paths simultaneously for synchronization to provide a seamless switchover, if one path fails.

Investigations on packet delay variations over the wireless channel

The increasing presence of wireless communication in factories has encouraged the introduction of novel applications on the factory floor. Highly accurate clock synchronization of wireless devices is necessary for timely communication between these devices and in some cases such as time-based localization, a major pre-requisite. One critical factor affecting synchronization performance is propagation delay variations suffered by a packet when it moves from its source to the destination. In this preliminary study, a set of measurements have been carried out to find out the extent of these variations. A highly accurate timestamping unit is used to detect the departure and arrival of a packet on the wireless channel, as the timestamping unit undergoes relative motion in an office environment. The results indicate that propagation delay variations are less affected by mobility than by reflections of signals from surrounding surfaces and objects. Future work will investigate whether the above observation is correct by employing higher speed mobility.

Synchronization robustness using Kalman-based clock servos

With the increasing deployment of large-scale distributed packet networks in the industry, highly reliable and precise clock synchronization gains even more importance to ensure timeliness of the exchanged datagrams. Design for reliability, robustness and availability should optimally be taken into account for the architecture of the synchronization subsystem as high-level redundancy schemes are limited in this respect. This work focuses on robustness of the clock servo subsystem and its sensitivity to disturbances, such as sudden changes of the packet delay, packet delay variation, environment of the oscillator, or packet loss. In particular, Kalman filter- and proportional-integral controller-steered clocks are investigated for their suitability for robust high-precision synchronization systems.

ToA ranging using subsample peak estimation and equalizer-based multipath reduction

In the presence of multipath propagation received signals are composed of multiple echoes which are correlated to the direct signal. When using bandlimited signals for time-of-arrival (ToA) locating in indoor environments, the radio bandwidth is often not sufficient to decompose the received signal and to identify the first arriving path. This paper presents a ToA estimation approach based on a high-resolution correlation receiver with subsample interpolation. It is combined with a multipath error estimator based on the inverse channel impulse response determined by an equalizer. Simulation results confirm that the proposed approach can reduce the multipath error by a factor of 3.42 compared to matched filtering. Finally, measurements using an FPGA-based prototype implementation for wireless LAN show the applicability of the proposed approach for real-time locating systems.

Timestamping of IEEE 802.15.4 CSS by CORDIC-based Chirp interpolation

Accurate timestamps of wireless frames are the basis for clock synchronization of distributed measurement devices as well as for time-based wireless localization. Wireless sensor networks (WSNs) benefit from both synchronization and localization as it enables the sensor node to fuse measurement data with temporal and spatial information. The lower communication layers of WSNs are often based on the IEEE 802.15.4 standard, whereas only for Ultra-wideband (UWB) timestamping and ranging abilities are specified. The Chirp Spread Spectrum (CSS) physical layer, recently introduced into IEEE 802.15.4-2011, is another promising modulation scheme for highly accurate timestamping. This paper presents a timestamping receiver architecture for 802.15.4 CSS based on a Delay-Locked Loop and subsample interpolation (chirp generation) using the CORDIC algorithm. This architecture generates arbitrary subsample- and frequency-shifted chirp templates on the fly and therefore does not require large correlation filters. Simulations of the timestamp performance show that the proposed architecture offers equal performance as post-correlation delay estimators, yet with a significantly reduced amount of multipliers. This facilitates the implementation of precision clock synchronization and localization into low-power wireless sensor nodes.

High precision and robustness in network-based clock synchronization using IEEE 1588

Network-based clock synchronization is an important prerequisite for many application areas and more and more required for the factory floor for network arbitration, control, and monitoring. Limitations of existing clock synchronization protocols are that they either support high redundancy and robustness or high precision. This paper presents an approach to integrate slave-side robustness into high precision clock synchronization. To achieve this goal, a system design facilitating the IEEE 1588 Precision Time Protocol (PTP) is proposed, which supports multiple masters in parallel and provides highly reliable and robust clock synchronization, while at the same time demanding no changes to the network and timing infrastructure. The slave-side robustness can be further enhanced to provide improved monitoring support for IEEE 1588. This makes the solution especially appealing for large-scale networks where retrofitting must be done efficiently and the network infrastructure is not under the control of the end device operator.

Out-of-band asymmetry removal for high accuracy clock synchronization in 100Base-TX

The IEEE 1588 standard enables accurate clock synchronization in a distributed network by synchronizing multiple slave clocks to one master. To reduce the synchronization offset, IEEE 1588 compensates for the propagation delay between master and slave by round-trip measurements and the assumption of known link asymmetries. Yet, the determination of the asymmetries is out of scope of the standard. Therefore, state-of-the-art implementations often neglect the presence of asymmetry which leads to a clock offset between master and slaves. In this paper we propose an asymmetry determination method for 100Base-TX using out-of-band Chirp Spread Spectrum signaling. In contrast to the round-trip measurements by IEEE 1588 event messages, the proposed solution is able to measure each individual link delay and is therefore capable of resolving the asymmetry. The practical feasibility of the proposed solution is shown by an FPGA-based prototype solution, which reveals that our approach enables sub-nanosecond synchronization even over (asymmetric) CAT5 cabling.